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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers 1. description the m37273m8-xxxsp and M37273MF-XXXSP are single-chip mi- crocomputers designed with cmos silicon gate technology. they have a osd, data slicer, and i 2 c-bus interface, so it is useful for a channel selection system for tv with a closed caption decoder. the features of the m37273e8sp and m37273efsp are similar to those of the m37273m8-xxxsp and M37273MF-XXXSP except that the chip has a built-in prom which can be written electrically. the difference between m37273m8-xxxsp and M37273MF-XXXSP are the rom size and ram size. accordingly, the following descriptions will be for the m37273m8-xxxsp. 2. features l number of basic instructions .................................................... 71 l memory size rom .............. 32k bytes (m37273m8-xxxsp, m37273e8sp) 60k bytes (M37273MF-XXXSP, m37273efsp) ram ............... 1152 bytes (m37273m8-xxxsp, m37273e8sp) 1472 bytes (M37273MF-XXXSP, m37273efsp) (*rom correction memory included) l minimum instruction execution time ......................................... 0.5 m s (at 8 mhz oscillation frequency) l power source voltage ................................................. 5 v 10 % l subroutine nesting ............................................. 128 levels (max.) l interrupts ....................................................... 17 types, 16 vectors l 8-bit timers .................................................................................. 6 l programmable i/o ports (ports p0, p1, p2, p3 0 , p3 1 ) ............. 26 l input ports (ports p5 0 , p5 1 ) ........................................................ 2 l output ports (ports p5 2 Cp5 7 ,p6) .............................................. 14 l 12 v withstand ports ................................................................... 6 l led drive ports ........................................................................... 4 l serial i/o ............................................................ 8-bit 5 1 channel l multi-master i 2 c-bus interface .............................. 1 (2 systems) l a-d comparator (6-bit resolution) ................................ 6 channels l pwm output circuit ......................................................... 8-bit 5 6 l power dissipation in high-speed mode ......................................................... 165 mw (at v cc = 5.5v, 8 mhz oscillation frequency, osd on, and data slicer on) in low-speed mode ......................................................... 0.33 mw (at v cc = 5.5v, 32 khz oscillation frequency) l rom correction function ................................................ 2 vectors l closed caption data slicer l osd function display characters ................................... 32 characters 5 2 lines (it is possible to display 3 lines or more by software) kinds of characters ........................................................ 254 kinds character display area ............................ cc mode: 16 5 26 dots osd mode: 16 5 20 dots kinds of character sizes ..................................... cc mode: 1 kind osd mode: 8 kinds kinds of character colors .................................. 8 colors (r, g, b) coloring unit ................... character, character background, raster display position horizontal: 128 levels vertical: 512 levels attribute ........................................................................................ cc mode: smooth italic, underline, flash, automatic solid space osd mode: border smoth roll-up window function 3. application tv with a closed caption decoder rev . 1.0
2 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 table of contents 1. description .......................................................................... 1 2. feautures ............................................................................. 1 3. application ............................................................................ 1 4. pin configuration .............................................................. 3 5. functional block diagram ............................................. 4 6. performance overview ................................................... 5 7. pin description ................................................................... 7 8. functional description ................................................. 11 8.1 central processing unit (cpu) .................... 11 8.2 memory .................................................................. 12 8.3 interrupts ........................................................... 18 8.4 timers ..................................................................... 23 8.5 serial i/o ................................................................ 26 8.6 multi-master i 2 c-bus interface .................... 29 8.7 pwm output circuit .......................................... 42 8.8 a-d comparator .................................................. 46 8.9 rom correction function ............................. 48 8.10 data slicer ......................................................... 49 8.11 osd functions ................................................... 60 8.11.1 display position ....................................... 65 8.11.2 dot size .................................................... 69 8.11.3 clock for osd .......................................... 70 8.11.4 field determination display ..................... 71 8.11.5 memory for osd ..................................... 73 8.11.6 character color ....................................... 77 8.11.7 character background color ................... 77 8.11.8 out1, out2 signals ............................... 78 8.11.9 attribute .................................................... 79 8.11.10 multiple display ...................................... 84 8.11.11 automatic solid space function ............ 85 8.11.12 window function ................................... 86 8.11.13 osd output pin control ........................ 88 8.11.14 raster coloring function ....................... 89 8.12. software runaway detect function ..... 91 8.13. reset circuit .................................................... 92 8.14. clock generating circuit ........................... 93 8.15. display oscillation circuit ........................ 96 8.16. auto-clear circuit ......................................... 96 8.17. addressing mode ............................................ 96 8.18. machine instructions ................................... 96 9. programming notes ........................................................ 96 10. absolute maximum ratings ......................................... 97 11. recommended operating conditions ..................... 97 12. electric characteristics .......................................... 98 13. a-d comparison characteristics ........................... 100 14. multi-master i 2 c-bus bus line characteristics ......... 100 15. prom programming method ..................................... 101 16. data required for mask orders ............................ 102 17. mask confirmation form ........................................... 103 18. mark specification form ........................................... 109 19. one time prom versions m37272e8sp/fp, m37272efsp marking ..................................................... 110 20. appendix ........................................................................... 111 21. package outline ........................................................... 136
3 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 4. pin configuration outline 52p4b fig. 4.1 pin configuration (top view) 22 23 24 25 26 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 p0 6 /int2/ad4 x out p5 0 /h sync p5 1 /v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 av cc hlf v hold cv in cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /ad1/int3 p1 6 /ad2 p3 0 /ad5 p3 1 /ad6 reset p2 6 /osc1/x cin p2 7 /osc2/x cout v cc p1 7 /ad3 p6 3 p6 4 p6 5 p6 6 p6 7 p5 6 p5 7 p6 0 p6 1 p6 2 m37273m8-xxxsp,M37273MF-XXXSP m37273e8sp,m37273efsp
4 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 5. functional block diagram fig. 5.1 functional block diagram of m37273 x in x out osc1/x cin osc2/x cout p0 (8) int1 int2 int3 p1 (8) pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 pwm tim2 tim3 24 25 30 19 27 26 23 cv in 22 21 20 v hold hlf 29 28 14 12 11 10 8 6 4 3 3 3 34 35 3 6 37 38 39 41 p2 (6) 18 17 16 43 45 i/o port p1 i/o port p2 p3 (2) 32 31 47 sda2 sda1 scl2 scl1 si/o s in s clk s out 49 50 51 52 2 output ports p5 2 ?5 7 output for display 1 h sync v sync r g b out1 out2 p1 0 i/o ports p3 0 , p3 1 ad1?d6 data slicer control signal clock input clock output x in x out reset input av cc v cc v ss cnv ss pins for data slicer clock output for osd/ sub-clock output i/o ports p2 6 , p2 7 clock input for osd/ sub-clock input a-d comparator 8-bit arithmetic and logical unit accumulator a (8) timer 6 t6 (8) timer 5 t5 (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit instruction register (8) instruction decoder crt circuit processor status register ps (8) stack pointer s (8) index register y (8) index register x (8) rom 32 k bytes program counter pc l (8) progam counter pc h (8) ram 1152 bytes data bus clock generating circuit reset cv in address bus i/o port p0 rom correction circuit multi-master i 2 c-bus interface input ports p5 0 , p5 1 synchronous signal input p5 (8) 75 44 46 48 15 13 9 p6 (8) 40 42 output ports p6
5 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d comparator pwm output circuit timers rom correction function subroutine nesting interrupt clock generating circuit data slicer rom ram osd rom osd ram p0 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 , p3 1 p5 0 , p5 1 p5 2 Cp5 5 ,p6 m37273m8-xxxsp, m37273e8sp M37273MF-XXXSP, m37273efsp m37273m8-xxxsp, m37273e8sp M37273MF-XXXSP, m37273efsp i/o i/o i/o i/o input output 71 0.5 m s (the minimum instruction execution time, at 8 mhz oscillation fre- quency) 8 mhz (maximum) 32k bytes 60k bytes 1152 bytes (rom correction memory included) 1472 bytes (rom correction memory included) 10k bytes 128 bytes 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins, int input pins, a-d input pin) 8-bit 5 1 (cmos input/output structure, however, n-channel open-drain output structure, when p1 1 Cp1 4 are used as multi-master i 2 c-bus inter- face, can be used as osd output pin, a-d input pins, int input pin, multi- master i 2 c-bus interface) 8-bit 5 1 (p2 is cmos input/output structure, however, n-channel open- drain output structure when p2 0 and 2 1 are used as serial output, can be used as serial input/output pins, timer external clock input pins, osd clock input/output pin, sub-clock input/output pins) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as a-d input pins) 2-bit 5 1 (can be used as osd input pins) 14-bit 5 1 (cmos output structure, can be used as osd output pins) 8-bit 5 1 1 (2 systems) 6 channels (6-bit resolution) 8-bit 5 6 8-bit timer 5 6 2 vectors 128 levels (maximum) <17 types> int external interrupt 5 3, internal timer interrupt 5 6, serial i/o interrupt 5 1, osd interrupt 5 1, multi-master i 2 c-bus interface interrupt 5 1, data slicer interrupt 5 1, f(x in )/4096 interrupt 5 1, v sync interrupt 5 1, brk instruction interrupt 5 1, reset 5 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) built-in parameter 6. performance overview table 6.1 performance overview functions
6 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 32 characters 5 2 lines cc mode: 16 5 20 dots (character display area : 16 5 20 dots) osd mode: 16 5 20 dots 254 kinds cc mode: 1 kinds osd mode: 8 kinds 1 screen: 8 kinds (per character unit) horizontal: 128 levels, vertical: 512 levels 5v 10% 165 mw typ. ( at oscillation frequency f(x in ) = 8 mhz, f osc = 27 mhz) 82.5 mw typ. ( at oscillation frequency f(x in ) = 8 mhz) 0.33 mw typ. ( at oscillation frequency f(x cin ) = 32 khz, f(x in ) = stopped) 0.055 mw ( maximum ) C10 c to 70 c cmos silicon gate process 52-pin plastic molded dip power source voltage power dissipation number of display characters dot structure kinds of characters kinds of character sizes 1 screen : 8 character font coloring display position functions table 6.2 performance overview (continued) osd function parameter in high-speed mode in low-speed mode in stop mode operating temperature range device structure package osd on osd off osd off data slicer on data slicer off data slicer off
7 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 pin name input/ functions output v cc , av cc , power source apply voltage of 5 v 10 % to (typical) v cc and av cc , and 0 v to v ss . v ss cnv ss cnv ss this is connected to v ss . ______ reset reset input input to enter the reset state, the reset input pin must be kept at a low for 2 m s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this low condition should be maintained for the required time. x in clock input input this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out clock output output x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. p0 0 /pwm0C i/o port p0 i/o port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually p0 5 /pwm5, programmed as input or output. at reset, this port is set to input mode. the output structure p0 6 /int2/ad4, is n-channel open-drain output. (see note 1) p0 7 /int1 pwm output output pins p0 0 Cp0 5 are also used as pwm output pins pwm0Cpwm5 respectively. the output structure is n-channel open-drain output. external interrupt input pins p0 6 and p0 7 are also used as int external interrupt input pins int2 and int1 respectively. input analog input input p0 6 pin is also used as analog input pin ad4. p1 0 /out2, i/o port p1 i/o port p1 is an 8-bit i/o port and has basically the same functions as port p0. the output p1 1 /scl1, structure is cmos output. (see note 1) p1 2 /scl2, osd output output pins p1 0 is also used as osd output pin out2. the output structure is cmos output. p1 3 /sda1, multi-master i/o pins p1 1 Cp1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master p1 4 /sda2, i 2 c-bus interface i 2 c-bus interface is used. the output structure is n-channel open-drain output. p1 5 /ad1/int3, analog input input pins p1 0 , p1 5 Cp1 7 are also used as analog input pin ad8, ad1Cad3 respectively. p1 6 /ad2, external interrupt input p1 5 pin is also used as int external interrupt input pin int3. p1 7 /ad3 input p2 0 /s clk , i/o port p2 i/o port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output p2 1 /s out , structure is cmos output. (see note 1) p2 2 /s in , serial i/o synchronous i/o p2 0 pin is also used as serial i/o synchronous clock input/output pin s clk . the output p2 3 /tim3, clock input/output port structure is n-channel open-drain output. p2 4 /tim2, serial i/o data i/o p2 1 pin is also used as serial i/o data output pin s out . the output structure is open-drain p2 5 , output output. p2 6 /osc1/ serial i/o data input input p2 2 pin is also used as serial i/o data input pin s in . x cin , external clock input pins p2 3 and p2 4 are also used as timer external clock input pins tim3 and tim2 p2 7 /osc2/ input for timer respectively. x cout clock input for osd input p2 6 pin is also used as osd clock input pin osc1. (see note 2) clock output for osd output p2 7 pin is also used as osd clock input pin osc2. the output structure is cmos output. (see note 2) sub-clock input input p2 6 pin is also used as sub-clock input pin x cin . sub-clock output output p2 7 pin is also used as sub-clock output pin x cout . 7. pin description table 7.1 pin description
8 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 pin name input/ functions output p3 0 /ad5, i/o port p3 i/o ports p3 0 and p3 1 are a 2-bit i/o port and has basically the same functions as port 0. p3 1 /ad6 the output structure can be selected either cmos output or n-channel open-drain output structure. (see notes 1, 3) analog input input pins p3 0 and p3 1 are also used as analog input pins ad5 and ad6 respectively. p5 0 /h sync , input port p5 input pin p5 0 and p5 1 are 2-bit input ports. p5 1 /v sync h sync input input pin p5 0 is also used as h sync input. this is a horizontal synchronous signal input for osd. v sync input input pin p5 1 is also used as v sync input. this is a vertical synchronous signal input for osd. p5 2 /r, output port p5 output ports p5 2 Cp5 7 are a 6-bit output port. the output structure is cmos output. p5 3 /g, p5 4 /b, osd output output pins p5 2 Cp5 5 are also used as osd output pins r, g, b, out1 respectively. the output p5 5 /out1 structure is cmos output. p5 6 , p5 7 p6 0 Cp6 7 output port p6 output port p6 is an 8-bit output port. the output structure is cmos output. cv in i/o for data slicer input input composite video signal through a capacitor. v hold input connect a capacitor between v hold and vss. hlf i/o connect a filter using of a capacitor and a resistor between hlf and vss. notes 1: port pi (i = 0 to 3) has the port pi direction register which can be used to program each bit as an input (0) or an output (1). the pins programmed as 1 in the direction register are output pins. when pins are programmed as 0, they are input pins. when pins are programmed as output pins, the output data are written into the port latch and then output. when data is read from the output pins, the output pin level is not read but the data of the port latch is read. this allows a previously-output value to be read correctly even if the output low voltage has risen, for example, because a light emitting diode was directly driven. the input pins are in the floating state, so the values of the pins can be read. when data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 2: to switch output functions, set the raster color register and osd control register. when pins p2 6 and p2 7 are used as the osd clock input/output pins, set the corresponding bits of the port p2 direction register to 0 (input mode). 3: to switch output structures, set bits 2 and 3 of the port p3 direction register, when 0, cmos output ; when 1, n-channel open-drain output. table 7.2 pin description (continued)
9 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 7.1 i/o pin block diagram (1) n-channel open-drain output ports p0 0 Cp0 5 note : each port is also used as follows : p0 0 Cp0 5 : pwm0Cpwm5 cmos output ports p1 , p2, p3 0 , p3 1 p o r t s p 1 , p 2 , p 3 0 , p 3 1 p o r t s p 0 0 p 0 5 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s notes 1: each port is also used as follows : p1 0 : out2 p1 1 : scl1 p1 2 : scl2 p1 3 : sda15 p1 4 : sda2 p1 5 : ad1/int3 p1 6 : ad2 p1 7 : ad3 2: the output structure of ports p3 0 and p3 1 can be selected either cmos output or n-channel open- drain output structure (when selecting n-channel open-drain, it is the same with p0 6 and p0 7 ). 3: the output structure of ports p1 1 Cp1 4 is n-channel open-drain output when using as multi-master i 2 c-bus interface (it is the same with p0 6 and p0 7 ). 4: the output structure of ports p2 0 and p2 1 is n-channel open-drain output when using as serial output (it is the same as p0 6 and p0 7 ). p2 0 : s clk p2 1 : s out p2 2 : s in p2 3 : tim3 p2 4 : tim2 p3 0 : ad5 p3 1 : ad6
10 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 i n t e r n a l c i r c u i t p 5 2 p 5 7 , p 6 p 5 0 , p 5 1 i n t e r n a l c i r c u i t p o r t s p 0 6 , p 0 7 d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s cmos input ports p5 0 , p5 1 note : each pin is also used as follows : p5 0 : h sync p5 1 : v sync fig. 7.2 i/o pin block diagram (2) cmos output ports p5 2 Cp5 7 , p6 note : each pin is also used as follows : p5 2 : r p5 3 : g p5 4 : b p5 5 : out1 n-channel open-drain output ports p0 6 , p0 7 note : each port is also used as follows : p0 6 : int2/ad4 p0 7 : int1
11 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8. functional description 8.1 central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 users manual for de- tails on the instruction set. machine-resident 740 family instructions are as follows: the fst, slw instruction cannot be used. the mul, div, wit and stp instructions can be used. 8.1.1 cpu mode register the cpu mode register contains the stack page selection bit and internal system clock selection bit. the cpu mode register is allo- cated at address 00fb 16 . fig. 8.1.1 cpu mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e s e t rw c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m ef u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( c m 2 ) ( s e e n o t e ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1 6 0 m a i n c l o c k ( x i n x o u t ) s t o p b i t ( c m 6 ) c p u m o d e r e g i s t e r ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw r w r w rw x c o u t d r i v a b i l i t y s e l e c t i o n b i t ( c m 5 ) 0 : l o w d r i v e 1 : h i g h d r i v e 0 : o s c i l l a t i n g 1 : s t o p p e d 7 0 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( c m 7 ) rw 0 : x i n x o u t s e l e c t e d ( h i g h - s p e e d m o d e ) 1 : x c i n x c o u t s e l e c t e d ( h i g h - s p e e d m o d e ) n o t e : t h i s b i t i s s e t t o 1 a f t e r t h e r e s e t r e l e a s e .
12 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.2 memory 8.2.1 special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. 8.2.2 ram ram is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 rom rom is used for storing user programs as well as the interrupt vector area. 8.2.4 osd ram ram for display is used for specifying the character codes and col- ors to display. 8.2.5 osd rom rom for display is used for storing character data. 8.2.6 interrupt vector area the interrupt vector area contains reset and interrupt vectors. 8.2.7 zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. 8.2.8 special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. 8.2.9 rom correction memory (ram) this is used as the program area for rom correction. fig. 8.2.1 memory map (m37273m8-xxxsp, m37273e8sp) 0000 16 00c0 16 00ff 16 sfr1 area ffff 16 ffde 16 ff00 16 0200 16 020f 16 sfr2 area 0300 16 00bf 16 0100 16 01ff 16 8000 16 rom correction function vector1: address 0300 16 vector2: address 0320 16 0320 16 rom (32k bytes) 087f 16 0800 16 osd ram (128 bytes) i see note j 05bf 16 3bff 16 1400 16 osd rom (10k bytes) ram (1152 bytes) ? m37273m8-xxxsp, m37273e8sp not used not used not used not used interrupt vector area special page note: refer to table 8.11.3 osd ram. 10000 16 1ffff 16 not used zero page
13 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.2.2 memory map (M37273MF-XXXSP, m37273efsp) 0000 16 00c0 16 00ff 16 sfr1 area ffff 16 ffde 16 ff00 16 0200 16 020f 16 sfr2 area not used 0300 16 00bf 16 0100 16 01ff 16 1000 16 rom correction function vector 1: address 0300 16 vector 2: address 0320 16 0320 16 rom (60k bytes) 10000 16 1ffff 16 087f 16 0800 16 osd ram (128 bytes) i see note j 06ff 16 13bff 16 11400 16 osd rom (10k bytes) ram (1472 bytes) ? M37273MF-XXXSP, m37273efsp not used not used interrupt vector area special page note: refer to table 8.11.3 osd ram. not used not used zero page
14 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.2.3 memory map of special function register 1 (sfr1) (1) n s f r 1 a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) d 0 1 6 d 1 1 6 d 2 1 6 d 3 1 6 d 4 1 6 d 5 1 6 d 6 1 6 d 7 1 6 d 8 1 6 d 9 1 6 d a 1 6 d b 1 6 d c 1 6 d d 1 6 d e 1 6 d f 1 6 c 0 1 6 c 1 1 6 c 2 1 6 c 3 1 6 c 4 1 6 c 5 1 6 c 6 1 6 c 7 1 6 c 8 1 6 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 c a 1 6 a d d r e s s p o r t p 5 ( p 5 ) c a p t i o n d a t a r e g i s t e r 3 ( c d 3 ) c a p t i o n d a t a r e g i s t e r 4 ( c d 4 ) o s d c o n t r o l r e g i s t e r ( o c ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( d 1 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) b l o c k c o n t r o l r e g i s t e r 1 ( b c 1 ) b l o c k c o n t r o l r e g i s t e r 2 ( b c 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 ( v p 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 ( v p 2 ) w i n d o w r e g i s t e r 1 ( w n 1 ) i n t e r r u p t i n p u t p o l a r i t y c o n t r o l r e g i s t e r ( r e ) b 7b 0 b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t b 7b 0 o s d p o r t c o n t r o l r e g i s t e r ( p f ) w i n d o w r e g i s t e r 2 ( w n 2 ) i / o p o l a r i t y c o n t r o l r e g i s t e r ( p c ) r a s t e r c o l o r r e g i s t e r ( r c ) : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? < s t a t e i m m e d i a t e l y a f t e r r e s e t > : 1 i m m e d i a t e l y a f t e r r e s e t : f i x t h i s b i t t o 0 ( d o n o t w r i t e 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t h i s b i t t o 1 ( d o n o t w r i t e 0 ) n a m e : 1 0 ? 0 0 1 6 ? 0 0 1 6 ? 0 0 1 6 ??000000 ? ? ? ? ? ? p f 2p f 3p f 4p f 5p f 7 ? ? ? ? i n t 1i n t 2i n t 3 ? p 3 0p 3 1 p 3 0 dp 3 1 dp 3 0 ct 3 s cp 3 1 c ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 4 0 1 6 o c 4 o c 5o c 2o c 3o c 0o c 1 o c 6 b c 1 0b c 1 1 b c 1 2b c 1 3b c 1 4b c 1 5 b c 1 6b c 1 7 b c 2 0b c 2 1b c 2 2b c 2 3b c 2 4b c 2 5 b c 2 6b c 2 7 v p 1 0v p 1 1v p 1 2v p 1 3v p 1 4v p 1 5 v p 1 6v p 1 7 v p 2 0v p 2 1v p 2 2v p 2 3v p 2 4v p 2 5 v p 2 6v p 2 7 w n 1 0w n 1 1w n 1 2w n 1 3w n 1 4w n 1 5w n 1 6w n 1 7 w n 2 0w n 2 1w n 2 2w n 2 3w n 2 4w n 2 5w n 2 6w n 2 7 r c 0r c 1r c 2r c 7 0 00 r c 3 r c 4 0 0 1 6 0 0 1 6 c d l 2 0c d l 2 1c d l 2 2c d l 2 3c d l 2 4c d l 2 5 c d l 2 6c d l 2 7 c d h 2 0c d h 2 1c d h 2 2c d h 2 3c d h 2 4c d h 2 5 c d h 2 6c d h 2 7 h p 4 h p 5 h p 2h p 3 h p 0 h p 1 h p 6 p c 4 p c 5 p c 2p c 3 p c 0 p c 1 p c 6 0 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 0 0 1 6 ( s e e n o t e 1 ) 0 0 1 6 ( s e e n o t e 2 ) n o t e s 1 : t h i s i s o n l y m 3 7 2 7 3 m f - x x x s p a n d m 3 7 2 7 3 e f s p . 2: a s f o r m 3 7 2 7 3 m 8 - x x x s p a n d m 3 7 2 7 3 e 8 s p , t h e r e s e t v a l u e i s ? ( i n d e t e r m i n a t e ) . p o r t p 6 ( p 6 )
15 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.2.4 memory map of special function register 1 (sfr1) (2) f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e 7 1 6 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 a d d r e s s s e r i a l i / o r e g i s t e r ( s i o ) a - d c o n t r o l r e g i s t e r 1 ( a d 1 ) t i m e r 5 ( t 5 ) t i m e r 6 ( t 6 ) t i m e r 1 ( t 1 ) c a p t i o n d a t a r e g i s t e r 1 ( c d 1 ) c a p t i o n p o s i t i o n r e g i s t e r ( c p s ) d a t a s l i c e r t e s t r e g i s t e r 2 c l o c k r u n - i n d e t e c t r e g i s t e r ( c r d ) d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) r e g i s t e r d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r m o d e r e g i s t e r 1 ( t m 1 ) t i m e r m o d e r e g i s t e r 2 ( t m 2 ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) d a t a s l i c e r t e s t r e g i s t e r 1 s y n c h r o n o u s s i g n a l c o u n t e r r e g i s t e r ( h c ) a - d c o n t r o l r e g i s t e r 2 ( a d 2 ) c p u m o d e r e g i s t e r ( c p u m ) b 7b 0 b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t b 7b 0 n s f r 1 a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) c a p t i o n d a t a r e g i s t e r 2 ( c d 2 ) s e r i a l i / o m o d e r e g i s t e r ( s m ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? < s t a t e i m m e d i a t e l y a f t e r r e s e t > : 1 i m m e d i a t e l y a f t e r r e s e t : f i x t h i s b i t t o 0 ( d o n o t w r i t e 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t h i s b i t t o 1 ( d o n o t w r i t e 0 ) n a m e : 1 0 t m 2 0 t m 2 1t m 2 2t m 2 3t m 2 4 t m 1 0 t m 1 1t m 1 2t m 1 3t m 1 4 c m 2 t m 1 r t m 2 rt m 3 rt m 4 ro s d rv s c r i n 3 r c k 0 i n 1 r d s r s 1 r t m 1 e t m 2 et m 3 et m 4 eo s d ev s c e i n 1 e d s es 1 ei n 2 e t m 2 5 0 0 1 6 f f 1 6 0 7 1 6 f f 1 6 0 7 1 6 0 7 1 6 t m 1 5t m 1 6t m 1 7 t m 2 6t m 2 7 ? s a d 0s a d 1s a d 2s a d 3s a d 4s a d 5s a d 6r b w l r ba d 0a a sa lp i nb bt r xm s t b c 0b c 1b c 2e s oa l s b s e l 0b s e l 1 c c r 0c c r 1c c r 2c c r 3c c r 4a c k 0 0 1 6 0 0 1 6 0 0 1 6 c k r i n 2 ri i c r t m 5 6 r i n 3 e c k ei i c e t m 5 6 et m 5 6 c 00 c m 7c m 5c m 6 s m 0s m 1s m 2s m 3 a d c 1 0a d c 1 1a d c 1 2a d c 1 4 a d c 2 0a d c 2 1a d c 2 2a d c 2 5 s m 5s m 6 a d c 2 4a d c 2 3 1 0 b i t s a d f a s t m o d e ? 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 d s c 1 0d s c 1 1d s c 1 2 d s c 2 0 d s c 2 3d s c 2 4d s c 2 5 c r d 3c r d 4c r d 5c r d 6c r d 7 d p s 3d p s 4d p s 5d p s 6d p s 7 c p s 0c p s 3c p s 4c p s 5c p s 1c p s 2c p s 6c p s 7 h c 0h c 3h c 4h c 5h c 1h c 2 0? 0? 0 ? ?? 00 0 ? 01100 01 1 00 00 1 0 1 00 00 0 0 1 6 c d h 1 0c d h 1 3c d h 1 4c d h 1 5c d h 1 1c d h 1 2c d h 1 6c d h 1 7 c d l 1 0c d l 1 3c d l 1 4c d l 1 5c d l 1 1c d l 1 2c d l 1 6c d l 1 7 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 d 1d 2d 3d 4d 5d 6d 7d 0 00 00?00 0 0 0 0 01 0 0? a c k b i t 0 9 1 6 3 c 1 6
16 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.2.5 memory map of special function register 2 (sfr2) 2 0 0 1 6 2 0 1 1 6 2 0 2 1 6 2 0 3 1 6 2 0 4 1 6 2 0 5 1 6 2 0 6 1 6 2 0 7 1 6 2 0 8 1 6 2 0 9 1 6 2 0 b 1 6 2 0 c 1 6 2 0 d 1 6 2 0 e 1 6 2 0 f 1 6 2 0 a 1 6 a d d r e s s p w m m o d e r e g i s t e r 2 ( p m 2 ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) p w m 2 r e g i s t e r ( p w m 2 ) p w m 4 r e g i s t e r ( p w m 4 ) p w m 5 r e g i s t e r ( p w m 5 ) r e g i s t e r p w m 0 r e g i s t e r ( p w m 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m m o d e r e g i s t e r 1 ( p m 1 ) r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) b 7b 0 b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t b 7b 0 n s f r 2 a r e a ( a d d r e s s e s 2 0 0 1 6 t o 2 0 f 1 6 ) p w m 3 r e g i s t e r ( p w m 3 ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? < s t a t e i m m e d i a t e l y a f t e r r e s e t > : 1 i m m e d i a t e l y a f t e r r e s e t : f i x t h i s b i t t o 0 ( d o n o t w r i t e 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t h i s b i t t o 1 ( d o n o t w r i t e 0 ) n a m e : 1 0 0 0 1 6 ? ? ? ? ? ? ? 0 0 1 6 p m 1 3 ? ?? ?0 ? ? 0 p m 1 0 p m 2 5p m 2 4p m 2 3p m 2 2p m 2 1p m 2 0 r c 0 r c 1 ? 0 0 1 6 0 0 1 6 0 0 1 6 ? 0 0 1 6 00 0 0 1 6 0 0 1 6
17 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.2.6 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i z cdbtv n?? ????? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0
18 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8.3 interrupts interrupts can be caused by 17 different sources consisting of 4 ex- ternal, 11 internal, 1 software, and reset. interrupts are vectored in- terrupts with priorities as shown in table 8.3.1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, ? the contents of the program counter and processor status regis- ter are automatically stored into the stack. the interrupt disable flag i is set to 1 and the corresponding interrupt request bit is set to 0. a the jump destination address stored in the vector address enters the program counter. other interrupts are disabled when the interrupt disable flag is set to 1. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figures 8.3.2 to 8.3.6 show the interrupt-related registers. interrupts other than the brk instruction interrupt and reset are ac- cepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be set to 0 by a program, but not set to 1. the interrupt enable bit can be set to 0 and 1 by a program. reset is treated as a non-maskable interrupt with the highest priority. figure 8.3.1 shows interrupt control. 8.3.1 interrupt causes (1) v sync , osd interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the osd interrupt occurs after character block display to the crt is completed. (2) int1 to int3 external interrupts the int1 to int3 interrupts are external interrupt inputs, the sys- tem detects that the level of a pin changes from low to high or from high to low, and generates an interrupt request. the in- put active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00dc 16 ) : when this bit is 0, a change from low to high is detected; when it is 1, a change from high to low is detected. note that both bits are cleared to 0 at reset. (3) timers 1 to 4 interrupts an interrupt is generated by an overflow of timers 1 to 4. vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff7 16 , fff6 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe9 16 , ffe8 16 ffe7 16 , ffe6 16 ffe5 16 , ffe4 16 ffe3 16 , ffe2 16 ffdf 16 , ffde 16 interrupt source reset osd interrupt int1 external interrupt data slicer interrupt serial i/o interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt int3 external interrupt int2 external interrupt multi-master i 2 c-bus interface interrupt timer 5 ? 6 interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable source switch by software (see note) non-maskable table 8.3.1 interrupt vector addresses and priority note: switching a source during a program causes an unnecessary interrupt. therefore, set a source at initializing of program.
19 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. (5) f(x in )/4096 interrupt the f (x in )/4096 interrupt occurs regularly with a f(x in )/4096 pe- riod. set bit 0 of the pwm mode register 1 to 0. (6) data slicer interrupt an interrupt occurs when slicing data is completed. (7) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (8) timer 5 ? 6 interrupt an interrupt is generated by an overflow of timer 5 or 6. their priorities are same, and can be switched by software. (9) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 8.3.1 interrupt control i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g i b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t
20 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.3.2 interrupt request register 1 fig. 8.3.3 interrupt request register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3 t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4o s d i n t e r r u p t r e q u e s t b i t ( o s d r ) 5v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 i n t 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( v s c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ? r r r r r r r r n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . b 7b 6 b 5 b 4b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i n i r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 d a t a s l i c e r i n t e r r u p t r e q u e s t b i t ( d s r ) 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i n 2 r ) 5 7f i x t h i s b i t t o 0 . 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . 0 0 ] 0 0 ] 0 ] 0 ] 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 6 ] r r r r ] r r ] r w f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( c k r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d m u l t i - m a s t e r i 2 c - b u s i n t e r r u p t r e q u e s t b i t ( i i c r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 6 t i m e r 5 6 i n t e r r u p t r e q u e s t b i t ( t m 5 6 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] r
21 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.3.4 interrupt control register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t c o n t r o l r e g i s t e r 1 0 t i m e r 1 i n t e r r u p t e n a b l e b i t ( t m 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 t i m e r 2 i n t e r r u p t e n a b l e b i t ( t m 2 e ) 2 t i m e r 3 i n t e r r u p t e n a b l e b i t ( t m 3 e ) 3 4 o s d i n t e r r u p t e n a b l e b i t ( o s d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 0 rw rw rw rw rw r 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . t i m e r 4 i n t e r r u p t e n a b l e b i t ( t m 4 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 v s y n c i n t e r r u p t e n a b l e b i t ( v s c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw 6 i n t 3 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i n 3 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw fig. 8.3.5 interrupt control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t c o n t r o l r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i n 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 d a t a s l i c e r i n t e r r u p t e n a b l e b i t ( d s e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i n 2 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 rw rw rw rw rw f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( c k e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t e n a b l e b i t ( i i c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw 6 t i m e r 5 ? 6 i n t e r r u p t e n a b l e b i t ( t m 5 6 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw 7 t i m e r 5 ? 6 i n t e r r u p t s w i t c h b i t ( t m 5 6 c ) 0 : t i m e r 5 1 : t i m e r 6 0rw
22 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.3.6 interrupt input polarity register b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register (re) [address 00dc 16 ] b name functions after reset r w interrupt input polarity register int1 polarity switch bit (int1) 0 0 0 0 : positive polarity 1 : negative polarity 0 4 0 : positive polarity 1 : negative polarity 5 4 to 7 int2 polarity switch bit (int2) int3 polarity switch bit (int3) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 rw rw rw r 0 : positive polarity 1 : negative polarity
23 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.4 timers this microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 8.4.3. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4, addresses 00ee 16 and 00ef 16 : timers 5 and 6), the value is also set to a timer, simultaneously. the count value is decremented by 1. the timer interrupt request bit is set to 1 by a timer overflow at the next count pulse, after the count value reaches 00 16 . 8.4.1 timer 1 timer 1 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? f(x in )/4096 or f(x cin )/4096 ? external clock from the tim2 pin the count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 1 interrupt request occurs at timer 1 overflow. 8.4.2 timer 2 timer 2 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? timer 1 overflow signal ? external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 timer 3 timer 3 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? f(x cin ) ? external clock from the tim3 pin the count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 . either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 timer 4 timer 4 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? f(x in )/2 or f(x cin )/2 ? f(x cin ) the count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00f5 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. timer 4 interrupt request occurs at timer 4 overflow. 8.4.5 timer 5 timer 5 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? timer 2 overflow signal ? timer 4 overflow signal the count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00f4 16 ) and bit 7 of the timer mode register 2 (address 00f5 16 ). when overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 5 interrupt request occurs at timer 5 overflow. 8.4.6 timer 6 timer 6 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? timer 5 overflow signal the count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 5 overflow signal is a count source for timer 6, the timer 5 functions as an 8-bit prescaler. timer 6 interrupt request occurs at timer 6 overflow. at reset, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. the f(x in ) ] /16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. however, the f(x in ) ] /16 is not selected as the timer 3 count source. so set both bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 to 0 before the execution of the stp instruction (f(x in ) ] /16 is selected as timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the internal clock is connected. as a result of the above procedure, the program can start under a stable clock. ] : when bit 7 of the cpu mode register (cm 7 ) is 1, f(x in ) becomes f(x cin ). the timer-related registers is shown in figures 8.4.1 and 8.4.2.
24 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.4.2 timer mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset rw timer mode register 2 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0rw 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 0 0 : f(x in )/16 or f(x cin )/16 (see note) 0 1 : f(x cin ) 1 0 : 11 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 0 0 : timer 3 overflow signal 0 1 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x in )/2 or f(x cin )/2 (see note) 1 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. fig. 8.4.1 timer mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tm10) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 5 of tm1 timer 2 count source selection bit 1 (tm11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tm12) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop timer 2 count source selection bit 2 (tm14) r 0 0 0 0 0 wr wr wr wr wr 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 timer 5 count source selection bit 2 (tm16) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 timer 6 internal count source selection bit (tm17) 0w r0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register.
25 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.4.3 timer block diagram timer 1 (8) 1/4096 1/2 cm7 tm15 1/8 timer 1 latch (8) 8 8 8 tm10 tm12 tm14 tm11 tm13 timer 2 (8) timer 2 latch (8) 8 8 8 timer 3 (8) timer 3 latch (8) 8 8 8 timer 4 (8) timer 4 latch (8) 8 8 8 timer 5 (8) timer 5 latch (8) 8 8 8 timer 6 (8) timer 6 latch (8) 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request timer 3 interrupt request reset stp instruction tm20 tm22 t3sc timer 4 interrupt request tm24 tm23 tm21 tm16 timer 5 interrupt request tm27 tm25 timer 6 interrupt request tm17 tm26 tm21 x cin x in tim2 tim3 selection gate: connected to black side at reset tm1 : timer mode register 1 tm2 : timer mode register 2 t3sc : timer 3 count source switch bit (address 00c7 16 ) cm : cpu mode register notes 1: high pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. ff 16 07 16 3: in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used.
26 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate: connect to black side at reset. synchronous circuit frequency divider 1/81/4 1/16 sm1 sm0 serial i/o counter (8) sm5 : lsb msb s sm2 1/2 x in s in s out s clk 1/2 x cin 1/2 cm7 1/2 note : when the data is set in the serial i/o register (address 00ea (see note) cm : cpu mode register sm : serial i/o mode register 16 ), the register functions as the serial i/o shift register. p2 0 latch sm3 p2 1 latch sm3 sm6 8.5 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in the clock synchronous mode. the serial i/o block diagram is shown in figure 8.5.1. the synchro- nous clock i/o pin (s clk ), and data output pin (s out ) also function as port p4, data input pin (s in ) also functions as port p2 0 Cp2 2 . bit 3 of the serial i/o mode register (address 00eb 16 ) selects whether the synchronous clock is supplied internally or externally (from the s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 8, 16, 32, or 64. to use the s in pin for serial i/o, set the corresponding bit of the port p2 direction register (address 00c5 16 ) to 0. fig. 8.5.1 serial i/o block diagram the operation of the serial i/o is described below. the operation of the serial i/o differs depending on the clock source; external clock or internal clock.
27 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 internal clock : the serial i/o counter is set to 7 during the write cycle into the serial i/o register (address 00ea 16 ), and the transfer clock goes high forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at high. at this time the interrupt request bit is set to 1. fig. 8.5.2 serial i/o timing (for lsb first) s y n c h r o n o u s c l o c k t r a n s f e r c l o c k s e r i a l i / o r e g i s t e r w r i t e s i g n a l s e r i a l i / o o u t p u t s o u t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ( n o t e ) s e r i a l i / o i n p u t s i n n o t e : w h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e s o u t p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d . i n t e r r u p t r e q u e s t b i t i s s e t t o 1 external clock : the an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has been counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 1 mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 8.5.2. when using an exter- nal clock for transfer, the external clock must be held at high for initializing the serial i/o counter. when switching between an inter- nal clock and an external clock, do not switch during transfer. also, be sure to initialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing instructions, such as seb and clb. 2: when an external clock is used as the synchronous clock, write trans- mit data to the serial i/o register when the transfer clock input level is high.
28 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.5.3 serial i/o mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 e b 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw s e r i a l i / o m o d e r e g i s t e r 0 , 1 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 o r f ( x c i n ) / 4 0 1 : f ( x i n ) / 1 6 o r f ( x c i n ) / 1 6 1 0 : f ( x i n ) / 3 2 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 p o r t f u n c t i o n s e l e c t i o n b i t ( s m 3 ) 4 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0 0 : p 2 0 , p 2 1 1 : s c l k , s o u t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : l s b f i r s t 1 : m s b f i r s t 6 f i x t h i s b i t t o 0 . 0 0 0 0 0 0 t r a n s f e r c l o c k i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n 1 : i n p u t s i g n a l f r o m s o u t p i n rw rw rw r w rw rw 0 7 f i x t h i s b i t t o 0 . 0r w
29 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 8.6.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency f : system clock = f(x in )/2 note : we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00f9 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). 8.6 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 8.6.1 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8.6.1 shows multi-master i 2 c-bus interface func- tions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 8.6.1 block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register (s1) b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 i 2 c control register (s1d) bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circuit eso 2 2
30 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.1 i 2 c data shift register the i 2 c data shift register (s0 : address 00f6 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00f9 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00f8 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. fig. 8.6.2 data shift register b 7b 6b 5b 4b 3b 2b 1b 0 i c d a t a s h i f t r e g i s t e r 1 ( s 0 ) [ a d d r e s s 0 0 f 6 1 6 ] b f u n c t i o n s a f t e r r e s e trw i c d a t a s h i f t r e g i s t e r 0 t o 7 t h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a . i n d e t e r m i n a t e 2 2 n o t e : 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n a m e d 0 t o d 7rw
31 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.2 i 2 c address register the i 2 c address register (address 00f7 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. (1) bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. (2) bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. fig. 8.6.3 i 2 c address register b 7b 6b 5b 4b 3b 2b 1b 0 0r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 f 7 1 6 ] b n a m e f u n c t i o n s 0 0 a f t e r r e s e t r w r r w
32 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.3 i 2 c clock control register the i 2 c clock control register (address 00fa 16 ) is used to set ack control, scl mode and scl frequency. (1) bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. (2) bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. (3) bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgement fig. 8.6.4 i 2 c address register (4) bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00fa 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0: standard clock mode 1: high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0: ack is returned. 1: ack is not returned. 0: no ack clock 1: ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 33303 setup disabled 25004 100 400 (see note) 05 83.3 16606 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 4000khz in the high-speed clock mode, the duty is as below . ??period : ??period = 3 : 2 in the other cases, the duty is as below. ??period : ??period = 1 : 1 setup value of ccr4 ccr0 rw rw rw rw
33 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.4 i 2 c control register the i 2 c control register (address 00f9 16 ) controls the data commu- nication format. (1) bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. (2) bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00f8 16 ). ? writing data to the i 2 c data shift register (address 00f6 16 ) is dis- abled. (3) bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to 8.6.5 i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. (4) bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00f7 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. (5) bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 8.6.5). fig. 8.6.5 connection port control by bsel0 and bsel1 note: set the corresponding direction register to 1 to use the port as multi-master i 2 c-bus interface. 0 1 b s e l 0 s c l / p 1 1 s c l 2 / p 1 2 0 1 b s e l 1 0 1 b s e l 0 s d a 1 / p 1 3 s d a 2 / p 1 4 0 1 b s e l 1 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e s c l s d a
34 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.6.6 i 2 c control register b 7b 6b 5b 4b 3b 2b 1b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g m o d e 1 : f r e e d a t a f o r m a t 5a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d a d d r e s s 0 0 f 9 1 6 ) i 2 c c o n t r o l r e g i s t e r b n a m e f u n c t i o n s a f t e r r e s e t r w n o t e : w h e n u s i n g p o r t s p 1 1 - p 1 4 a s i c - b u s i n t e r f a c e , t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m c m o s o u t p u t t o n - c h a n n e l o p e n - d r a i n o u t p u t . 2 2 r w r w r w r w r w
35 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.5 i 2 c status register the i 2 c status register (address 00f8 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). (2) bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition. ] general call: the master transmits the general call address 00 16 to all slaves. (3) bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. n in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start con- dition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00f7 16 ). ? a general call is received. n in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address regis- ter (8 bits consists of slave address and rbw), the first bytes match. n the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). (4) bit 3: arbitration lost ] detecting flag (al) n the master transmission mode, when a device other than the mi- crocomputer sets the sda to l,, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to 0. when arbitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ] arbitration lost: the status in which communication as a master is disabled. (5) bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 8.6.8 shows an interrupt request sig- nal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00f6 16 ). ? when the eso bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception (6) bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (see note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 c control register (address 00f9 16 ) is 0 and at reset, the bb flag is kept in the 0 state. (7) bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00f9 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 (trans- ___ mit) if the least significant bit (r/w bit) of the address data transmit- ___ ted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset
36 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 (8) bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when arbitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset fig. 8.6.7 i 2 c status register b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 f 8 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : s l a v e r e c i e v e m o d e 0 1 : s l a v e t r a n s m i t m o d e 1 0 : m a s t e r r e c i e v e m o d e 1 1 : m a s t e r t r a n s m i t m o d e 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b u s f r e e 1 : b u s b u s y b u s b u s y f l a g ( b b ) 0 : i n t e r r u p t r e q u e s t i s s u e d 1 : n o i n t e r r u p t r e q u e s t i s s u e d i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n o t d e t e c t e d 1 : d e t e c t e d a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : a d d r e s s m i s m a t c h 1 : a d d r e s s m a t c h s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o g e n e r a l c a l l d e t e c t e d 1 : g e n e r a l c a l l d e t e c t e d g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l a s t b i t = 0 1 : l a s t b i t = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) fig. 8.6.8 interrupt request signal generation timing s c l p i n i i c i r q note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output, when the following condition is satisfied: a start condition is set by another master device.
37 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.6 start condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is 1, execute a write instruction to the i 2 c status register (address 00f8 16 ) to set the mst, trx and bb bits to 1. a start condition will then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 8.6.9 for the start condition generation timing diagram, and table 8.6.2 for the start condition/ stop condition generation timing table. fig. 8.6.9 start condition generation timing diagram i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e s e t u p t i m e s c l s d a b b f l a g s e t t i m e f o r b b f l a g 8.6.7 stop condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is 1, execute a write instruction to the i 2 c status register (address 00f8 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition genera- tion timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 8.6.10 for the stop condition generation timing diagram, and table 8.6.2 for the start condition/stop condition generation timing table. fig. 8.6.10 stop condition generation timing diagram table 8.6.2 start condition/stop condition generation tim- ing table item setup time (start condition) setup time (stop condition) hold time set/reset time for bb flag standard clock mode 5.0 m s (20 cycles) 4.25 m s (17 cycles) 5.0 m s (20 cycles) 3.0 m s (12 cycles) high-speed clock mode 2.5 m s (10 cycles) 1.75 m s (7 cycles) 2.5 m s (10 cycles) 1.5 m s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e s e t u p t i m e s c l s d a b b f l a g r e se t t i m e f o r b b f l a g
38 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.8 start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 8.6.11 and table 8.6.3. only when the 3 conditions of table 8.6.3 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq is generated to the cpu. fig. 8.6.11 start condition/stop condition detect timing dia- gram standard clock mode 6.5 m s (26 cycles) < scl release time 3.25 m s (13 cycles) < setup time 3.25 m s (13 cycles) < hold time high-speed clock mode 1.0 m s (4 cycles) < scl release time 0.5 m s (2 cycles) < setup time 0.5 m s (2 cycles) < hold time table 8.6.3 start condition/stop condition detect conditions note: absolute time at f = 4 mhz. the value in parentheses denotes the num- ber of f cycles. h o l d t i m e s e t u p t i m e s c l s d a ( s t a r t c o n d i t i o n ) s d a ( s t o p c o n d i t i o n ) s c l r e l e a s e t i m e h o l d t i m e s e t u p t i m e 8.6.9 address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. (1) 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00f7 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 8.6.12, (1) and (2). (2) 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to 1. an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, an address com- parison between the rbw bit of the i 2 c address register (address 00f7 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00f8 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00f6 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00f7 16 ) to 1 by software. this processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00f7 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 8.6.12, (3) and (4).
39 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.6.10 example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and 0 in the rbw bit. ? set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 00fa 16 ). ? set 10 16 in the i 2 c status register (address 00f8 16 ) and hold the scl at the high. set a communication enable status by setting 48 16 in the i 2 c control register (address 00f9 16 ). ? set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00f6 16 ) and set 0 in the least significant bit. a set f0 16 in the i 2 c status register (address 00f8 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. d set transmit data in the i 2 c data shift register (address 00f6 16 ). at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step d . ? set d0 16 in the i 2 c status register (address 00f8 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. 8.6.11 example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and 0 in the rbw bit. ? set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 00fa 16 ). ? set 10 16 in the i 2 c status register (address 00f8 16 ) and hold the scl at the high. set a communication enable status by setting 48 16 in the i 2 c control register (address 00f9 16 ). ? when a start condition is received, an address comparison is made. a ?when all transmitted address are0 (general call): ad0 of the i 2 c status register (address 00f8 16 ) is set to 1and an interrupt request signal occurs. ?when the transmitted addresses match the address set in ? : ass of the i 2 c status register (address 00f8 16 ) is set to 1 and an interrupt request signal occurs. ?in the cases other than the above: ad0 and aas of the i 2 c status register (address 00f8 16 ) are set to 0 and no interrupt request signal occurs. d set dummy data in the i 2 c data shift register (address 00f6 16 ). ? when receiving control data of more than 1 byte, repeat step d . ? when a stop condition is detected, the communication ends.
40 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.6.12 address data communication format ss l a v e a d d r e s s a d a t aa d a t aa / a p r / w 7 b i t s 0 ? t o 8 b i t s1 t o 8 b i t s ss l a v e a d d r e s s a d a t a ad a t a ap 7 b i t s 1 ? t o 8 b i t s1 t o 8 b i t s ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s 1 s t 7 b i t s a a d a t a 7 b i t s 0 ? b i t s1 t o 8 b i t s ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r s l a v e a d d r e s s 2 n d b y t e a d a t aa / a p 1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s a a 7 b i t s 0 ? b i t s7 b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e d a t a 1 t o 8 b i t s s r s l a v e a d d r e s s 1 s t 7 b i t s a d a t a a p 1 t o 8 b i t s 1 ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s:s t a r t c o n d i t i o np : s t o p c o n d i t i o n a:a c k b i tr / w : r e a d / w r i t e b i t s r:r e s t a r t c o n d i t i o n f r o m m a s t e r t o s l a v e f r o m s l a v e t o m a s t e r r / w r / w r / w r / w 8.6.12 precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the raead-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0) when executing the read-modify-write instruction for this register during transfer, data may become a value not intended. ?i 2 c address register (s0d) when the read-modify-write instruction is executed for this register at detecting the stop condition, data may become a value not ______ intended. it is because hardware changes the read/write bit (rbw) at the above timing. ?i 2 c status register (s1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ?i 2 c control register (s1d) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended. because hardware changes the bit counter (bc0Cbc2) at the above timing. ?i 2 c clock control register (s2) the read-modify-write instruction can be executed for this register. (2) start condition generating procedure us- ing multi-master ? procedure example (the necessary conditions of the generating procedure are described as the following ? to ? ). ? ? lda ( taking out of slave address value) sei (interrupt disabled) bbs 5,s1,busbusy (bb flag confirming and branch process) busfree: sta s0 ( writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) ? ? busbusy: cli (interrupt enabled) ? ? ? use sta, stx or sty of the zero page addressing instruction for writing the slave address value to the i 2 c data shift register. ? use ldm instruction for setting trigger of start condition gener- ating. write the slave address value of above ? and set trigger of start condition generating of above ? continuously shown the above procedure example. ? disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately.
41 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 (3) restart condition generating procedure ? procedure example (the necessary conditions of the generating procedure are described as the following ? to a .) execute the following procedure when the pin bit is 0. ? ? ldm #$00, s1 (select slave receive mode) lda ( taking out of slave address value) sei (interrupt disabled) sta s0 ( writing of slave address value) ldm #$f0, s1 (trigger of restart condition generating) cli (interrupt enabled) ? ? ? select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the sda pin is released. ? the scl pin is released by writing the slave address value to the i 2 c data shift register. use sta, stx or sty of the zero page addressing instruction for writing. use ldm instruction for setting trigger of restart condition gen- erating. ? write the slave address value of above ? and set trigger of re- start condition generating of above continuously shown the above procedure example. a disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) stop condition generating procedure ? procedure example (the necessary conditions of the generating procedure are described as the following ? to .) ? ? sei (interrupt disabled) ldm #$c0, s1 (select master transmit mode) nop (set nop) ldm #$d0, s1 (trigger of stop condition generating) cli (interrupt enabled) ? ? ? write 0 to the pin bit when master transmit mode is select. ? execute nop instruction after setting of master transmit mode. also, set trigger of stop condition generating within 10 cycles af- ter selecting of master trasmit mode. disable interrupts during the following two process steps: ? select of master transmit mode ? trigger of stop condition generating (5) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simultaneously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not ex- ecute an instruction to set the mst and trx bits to 0 from 1 si- multaneously when the pin bit is 1. it is because it may become the same as above. (6) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem.
42 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.7 pwm output function this microcomputer is equipped with six 8-bit pwms (pwm0C pwm5). pwm0Cpwm5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 m s (for f(x in ) = 8 mhz) and repeat period of 1024 m s (for f(x in ) = 8 mhz). figure 8.7.1 shows the pwm block diagram. the pwm timing gen- erating circuit applies individual control signals to pwm0Cpwm5 us- ing f(x in ) divided by 2 as a reference signal. 8.7.1 data setting when outputting pwm0Cpwm5, set 8-bit output data to the pwmi register (i means 0 to 5; addresses 0200 16 to 0205 16 ). 8.7.2 transmitting data from register to pwm circuit data transfer from the 8-bit pwm register to the 8-bit pwm circuit is executed at writing data to the register. the signal output from the 8-bit pwm output pin corresponds to the contents of this register. 8.7.3 operating of 8-bit pwm the following explains pwm operation. first, set the bit 0 of pwm mode register 1 (address 0208 16 ) to 0 (at reset, bit 0 is already set to 0 automatically), so that the pwm count source is supplied. pwm0Cpwm5 are also used as pins p0 0 Cp0 5 . set the correspond- ing bits of the port p0 direction register to 1 (output mode). and select each output polarity by bit 3 of pwm mode register 1 (address 0208 16 ). then, set bits 5 to 0 of pwm mode register 2 (address 0209 16 ) to 1 (pwm output). the pwm waveform is output from the pwm output pins by setting these registers. figure 17 shows the 8-bit pwm timing. one cycle (t) is composed of 256 (2 8 ) segments. the 8 kinds of pulses relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 17 (a). the 8-bit pwm outputs waveform which is the logical sum (or) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit pwm register. several examples are shown in figure 17 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm register. a length of entirely high cannot be output, i.e. 256/256. 8.7.4 output after reset at reset, the output of ports p0 0 Cp0 5 is in the high-impedance state, and the contents of the pwm register and the pwm circuit are unde- fined. note that after reset, the pwm output is undefined until setting the pwm register.
43 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.7.1 pwm block diagram 1/2 pm10 x in b7 b0 8 pm13 p0 0 pm20 d0 0 pwm0 p0 1 pm21 d0 1 pwm1 p0 2 pm22 d0 2 pwm2 p0 3 pm23 d0 3 pwm3 p0 4 pm24 d0 4 pwm4 p0 5 pm25 d0 5 pwm5 pm1 pm2 p0 d0 : pwm mode register 1 (address 0208 16 ) : pwm mode register 2 (address 0209 16 ) : port p0 register (address 00c0 16 ) : port p0 direction register (address 00c1 16 ) selection gate: connected to black side at reset. is as same contents with the others. pwm1 register (address 0201 16 ) pwm2 register (address 0202 16 ) pwm3 register (address 0203 16 ) pwm4 register (address 0204 16 ) pwm5 register (address 0205 16 ) pwm timing generating circuit data bus pwm0 register (address 0200 16 ) 8-bit pwm circuit inside of
44 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.7.2 pwm timing (a) pulses showing the weight of each bit 13579 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 1 2 20 28 3 6 4 4 5 2 60 6 8 7 6 8 4 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 8 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 128 bit 0 pwm output t = 4 m s t = 1024 m s f(x in ) = 8 mhz (b) example of 8-bit pwm t 00 16 (0) 01 16 (1) 18 16 (24) ff 16 (255) t = 256 t
45 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pm2) [address 0209 16 ] b after reset rw pwm mode register 2 0 1 2 3 4 0 name functions p0 0 /pwm0 output selection bit (pm20) 0 : p0 0 output 1 : pwm0 output p0 2 /pwm2 output selection bit (pm22) 0 : p0 2 output 1 : pwm2 output p0 3 /pwm3 output selection bit (pm23) 0 : p0 3 output 1 : pwm3 output p0 4 /pwm4 output selection bit (pm24) 0 : p0 4 output 1 : pwm4 output 5 p0 5 /pwm5 output selection bit (pw25) 0: p0 5 output 1: pwm5 output 6, 7 fix these bits to ?. p0 1 /pwm1 output selection bit (pm21) 0 : p0 1 output 1 : pwm1 output 0 0 0 0 0 0 rw rw rw rw rw rw rw 00 fig. 8.7.3 pwm mode register 1 fig. 8.7.4 pwm mode register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m m o d e r e g i s t e r 1 ( p m 1 ) [ a d d r e s s 0 2 0 8 1 6 ] b a f t e r r e s e t rw p w m m o d e r e g i s t e r 1 0 1 , 2 3 0 n a m ef u n c t i o n s p w m o u t p u t p o l a r i t y s e l e c t i o n b i t ( p m 1 3 ) i n d e t e r m i n a t e 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y r w r rw p w m c o u n t s s o u r c e s e l e c t i o n b i t ( p m 1 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p 4 t o 7 i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r
46 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.8 a-d comparator a-d comparator consists of 6-bit d-a converter and comparator. a-d comparator block diagram is shown in figure 8.8.1. the reference voltage v ref for d-a conversion is set by bits 0 to 5 of a-d control register 2 (address 00ed 16 ). the comparison result of the analog input voltage and the reference voltage v ref is stored in bit 4 of a-d control register 1 (address 00ec 16 ). for a-d comparison, set 0 to corresponding bits of the direction register to use ports as analog input pins. write the data for select of analog input pins to bits 0 to 2 of a-d control register 1 and write the digital value corresponding to v ref to be compared to the bits 0 to 5 of a-d control register 2. the voltage comparison starts by writ- ing to a-d control register 2, and it is completed after 16 machine cycles (nop instruction 5 8). fig. 8.8.1 a-d comparator block diagram a-d control register 1 bits 0 to 2 comparator control data bus bit 4 switch tree a-d control register 2 resistor ladder compa- rator analog signal switch bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a-d control register 1 ad1 ad2 ad3 ad4 ad5 ad6
47 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.8.2 a-d control register 1 b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n t r o l r e g i s t e r 1 ( a d 1 ) [ a d d r e s s 0 0 e c 1 6 ] b a f t e r r e s e t rw a - d c o n t r o l r e g i s t e r 1 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d c 1 0 t o a d c 1 2 ) n a m ef u n c t i o n s b 2 b 1 b 0 0 0 0 : a d 1 0 0 1 : a d 2 0 1 0 : a d 3 0 1 1 : a d 4 1 0 0 : a d 5 1 0 1 : a d 6 1 1 0 : 1 1 1 : 4 s t o r a g e b i t o f c o m p a r i s o n r e s u l t ( a d c 1 4 ) 0 : i n p u t v o l t a g e < r e f e r e n c e v o l t a g e 1 : i n p u t v o l t a g e > r e f e r e n c e v o l t a g e 0 i n d e t e r m i n a t e 0 d o n o t s e t . 3t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . rw rw r 0 5 t o 7 n o t h i n g i s a s s i g n e d . t h i s b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r fig. 8.8.3 a-d control register 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2 (ad2) [address 00ed 16 ] b after reset rw a-d control register 2 0 to 5 6, 7 0 0 name functions d-a converter set bits (adc20 to adc25) b0b1b2 b3 b4 b5 nothing is assigned. these bits are write disable bits. when these bits are reed out, the values are ?0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128vcc : 5/128vcc : 123/128vcc : 125/128vcc : 127/128vcc : 1/128vcc rw r
48 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.9.2 rom correction enable register fig. 8.9.1 rom correction address registers 8.9 rom correction function this can correct program data in rom. up to 2 addresses can be corrected, a program for correction is stored in the rom correction vector in ram as the top address. the rom correction vectors are 2 vectors. vector 1 : address 0300 16 vector 2 : address 0320 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the rom correction vector as the top address, the main program branches to the correction program stored in the rom memory for correction. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. the rom correction function is controlled by the rom correction enable register. notes 1: specify the first address (op code address) of each instruction as the rom correction address. 2: use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3: do not set the same rom correction address to vectors 1 and 2. 020a 16 rom correction address 1 (high-order) 020b 16 rom correction address 1 (low-order) 020c 16 rom correction address 2 (high-order) 020d 16 rom correction address 2 (low-order) b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 020e 16 ] b after reset rw rom correction enable register 0 vector 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 vector 2 enable bit (rc1) 0: disabled 1: enabled 2 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?.? 0 0 0 rw rw r
49 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10 data slicer this microcomputer includes the data slicer function for the closed caption decoder (referred to as the ccd). this function takes out the caption data superimposed in the vertical blanking interval of a com- posite video signal. a composite video signal which makes the sync chips polarity negative is input to the cv in pin. when the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00e0 16 ) to 0. these set- tings can realize the low-power dissipation. fig. 8.10.1 data slicer block diagram composite video signal 1 m w sync pulse counter register (address 00e9 16 ) data slicer control register 2 (address 00e1 16 ) data slicer control register 1 (address 00e0 16 ) clock run-in defect register (address 00e4 16 ) caption position register (address 00e6 16 ) data clock position register (address 00e5 16 ) interrupt request generating circuit data slicer interrupt request synchronizing signal counter synchronizing separation circuit sync slice circuit clamping circuit low-pass filter timing signal generating circuit clock run-in determination circuit data slice line specification circuit start bit detecting circuit data clock generating circuit 16-bit shift register caption data register 1 (address 00e2 16 ) caption data register 2 (address 00e3 16 ) data bus comparator 0.1 m f 470 w 560 pf cv in 1 m f 1 k w 200 pf h sync hlf + reference voltage generating circuit v hold 1000 pf high-order low-order data slicer on/off caption data register 4 (address 00cf 16 ) caption data register 3 (address 00ce 16 ) external circuit note : make the length of wiring which is connected to v hold , hlf, and cv in pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.
50 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.1 notes when not using data slicer when bit 0 of data slicer control register 1 (address 00e0 16 ) is 0, terminate the pins as shown in figure 8.10.2. fig. 8.10.2 termination of data slicer input/output pins when data slicer circuit and timing generating circuit is in off state when both bits 0 and 2 of data slicer control register 1 (address 00e0 16 ) are 1, terminate the pins as shown in figure 8.10.3. fig. 8.10.3 termination of data slicer input/output pins when timing signal generating circuit is in on state av cc hlf v hold cv in apply the same voltage as v cc to av cc pin. open open leave hlf pin open. leave v hold pin open. pull-down cv in pin to v ss through a resistor of 5 k w or more. 5 k w or more 19 20 21 22 apply the same voltage as v cc to av cc pin. connect the same external circuit as when using data slicer to hlf pin. leave v hold pin open. pull-up cv in to v cc through a resistor of 5 k w or more. av cc v hold cv in open 5 k w or more hlf 1 k w 200pf1 m f 19 20 21 22
51 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 figures 8.10.4 and 8.10.5 the data slicer control registers. fig. 8.10.4 data slicer control register 1 fig. 8.10.5 data slicer control register 2 b 7b 6b 5b 4b 3b 2b 1b 0 d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) [ a d d r e s s 0 0 e 0 1 6 ] d a t a s l i c e r c o n t r o l r e g i s t e r 1 00 rw 0rw 2r e f e r e n c e c l o c k s o u r c e s e l e c t i o n b i t ( d s c 1 2 ) 0 : v i d e o s i g n a l 1 : h s y n c s i g n a l 0r w 0rw 0 rw 11 0 : s t o p p e d 1 : o p e r a t i n g d a t a s l i c e r a n d t i m i n g s i g n a l g e n e r a t i n g c i r c u i t c o n t r o l b i t ( d s c 1 0 ) f i x t h e s e b i t s t o 0 . 3 , 4 000 10 : f 2 1 : f 1 s e l e c t i o n b i t o f d a t a s l i c e r e f e r e n c e v o l t a g e g e n e r a t i n g f i e l d ( d s c 1 1 ) f i x t h e s e b i t s t o 1 . 5 , 6 d e f i n i t i o n o f f i e l d s 1 ( f 1 ) a n d 2 ( f 2 ) h s e p v s e p f 1 : h s e p v s e p f 2 : b a f t e r r e s e t r w n a m ef u n c t i o n s 0rw f i x t h i s b i t t o 0 . 7 b 7b 6b 5b 4b 3b 2b 1b 0 d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) [ a d d r e s s 0 0 e 1 1 6 ] r w d a t a s l i c e r c o n t r o l r e g i s t e r 2 0i n d e t e r m i n a t e r 1 0r w i n d e t e r m i n a t er i n d e t e r m i n a t er 01 0 : d a t a i s n o t l a t c h e d y e t a n d a c l o c k - r u n - i n i s n o t d e t e r m i n e d . 1 : d a t a i s l a t c h e d a n d a c l o c k - r u n - i n i s d e t e r m i n e d . c a p t i o n d a t a l a t c h c o m p l e t i o n f l a g 1 ( d s c 2 0 ) f i x t h i s b i t t o 1 . 2r e a d - o n l y t e s t b i t 30 : f 2 1 : f 1 f i e l d d e t e r m i n a t i o n f l a g ( d s c 2 3 ) 40 : m e t h o d ( 1 ) 1 : m e t h o d ( 2 ) v e r t i c a l s y n c h r o n o u s s i g n a l ( v s e p ) g e n e r a t i n g m e t h o d s e l e c t i o n b i t ( d s c 2 4 ) 0rw 50 : m a t c h 1 : m i s m a t c h v - p u l s e s h a p e d e t e r m i n a t i o n f l a g ( d s c 2 5 ) i n d e t e r m i n a t er 6 0 rw f i x t h i s b i t t o o . b a f t e r r e s e t f u n c t i o n sn a m e d e f i n i t i o n o f f i e l d s 1 ( f 1 ) a n d 2 ( f 2 ) h s e p v s e p f 1 : h s e p v s e p f 2 : r 7 r e a d - o n l y t e s t b i t i n d e t e r m i n a t e
52 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.2 clamping circuit and low-pass filter the clamp circuit clamps the sync chip part of the composite video signal input from the cv in pin. the low-pass filter attenuates the noise of clamped composite video signal. the cv in pin to which composite video signal is input requires a capacitor (0.1 m f) coupling outside. pull down the cv in pin with a resistor of hundreds of kiloohms to 1 m w . in addition, we recommend to install externally a simple low- pass filter using a resistor and a capacitor at the cv in pin (refer to figure 8.10.1). 8.10.3 sync slice circuit this circuit takes out a composite sync signal from the output signal of the low-pass filter. 8.10.4 synchronous signal separation circuit this circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1)horizontal synchronous signal (h sep ) a one-shot horizontal synchronizing signal hsep is generated at the falling edge of the composite sync signal. (2)vertical synchronous signal (v sep ) as a v sep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 00e1 16 ). ?method 1 the low level width of the composite sync signal is measured. if this width exceeds a certain time, a v sep signal is generated in synchronization with the rising of the timing signal immediately after this low level. ?method 2 the low level width of the composite sync signal is measured. if this width exceeds a certain time, it is detected whether a falling of the composite sync sig- nal exits or not in the low level period of the timing signal immediately after this low level. if a falling exists, a v sep signal is generated in synchronization with the rising of the timing signal (refer to figure 8.10.6). figure 8.10.6 shows a v sep generating timing. the timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. reading bit 5 of data slicer control register 2 permits determinating the shape of the v-pulse portion of the composite sync signal. as shown in figure 8.10.7, when the a level matches the b level, this bit is 0. in the case of a mismatch, the bit is 1. fig. 8.10.6 vsep generating timing (method 2) c o m p o s i t e s t i m i n g s i g n a l v s e p s i g n a l m e a s u r e l o w p e r i o d a v s e p s i g n a l i s g e n e r a t e d a t a r i s i n g o f t h e t i m i n g s i g n a l i m m e d i a t e l y a f t e r t h e l o w l e v e l w i d t h o f t h e c o m p o s i t e s y n c s i g n a l e x c e e d s a c e r t a i n t i m e .
53 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.5 timing signal generating circuit this circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. it also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. the circuit operates by setting bit 0 of data slicer control register 1 (address 00e0 16 ) to 1. the reference clock can be used as a display clock for osd function in addition to the data slicer. the h sync signal can be used as a count source instead of the composite sync signal. however, when the h sync signal is selected, the data slicer cannot be used. a count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00e0 16 ). for the pins hlf, connect a resistor and a capacitor as shown in figure 8.10.1. make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be gener- ated. note: it takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. in this period, various timing signals, h sep signals and v sep sig- nals become unstable. for this reason, take stabilization time into con- sideration when programming. fig. 8.10.7 determination of v-pulse waveform composite sync signal ab 0 1 1 bit 5 of dsc2
54 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.6 data slice line specification circuit (1) specification of data slice line this circuit decides a line on which caption data is superimposed. the line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (f1 and f2) are sliced their data. the caption position register (address 00e6 16 ) is used for each setting (refer to table 8.10.1). the counter is reset at the falling edge of v sep and is incremented by 1 every h sep pulse. when the counter value matched the value specified by bits 4 to 0 of the caption position register, this h sep is sliced. the values of 00 16 to 1f 16 can be set in the caption position register (at setting only 1 appropriate line). figure 8.10.8 shows the signals in the vertical blanking interval. figure 8.10.9 shows the structure of the caption position register. (2) specification of line to set slice voltage the reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to table 8.10.1). the field to generate slice voltage is specified by bit 1 of data slicer control register 1. the line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to table 8.10.1). fig. 8.10.8 signals in vertical blanking interval (3) field determination the field determination flag can be read out by bit 3 of data slicer control register 2. this flag charge at the falling edge of v sep . video signal vertical blanking interval composite video signal count value to be set in the caption position register (?f 16 ?in this case) h sep v sep h sep magnified drawing clock run-in start bit + 16-bit data start bit window for deteminating clock-run-in composite video signal line 21 1 appropriate line is set by the caption position register (when setting line 19)
55 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.10.9 caption position register field and line to generate slice voltage ? field specified by bit 1 of dsc1 ? line 21 (total 1 line) ? field specified by bit 1 of dsc1 ? a line specified by bits 4 to 0 of cps (total 1 line) (see note 3) ? field specified by bit 1 of dsc1 ? line 21 (total 1 line) ? field specified by bit 1 of dsc1 ? line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) field and line to be sliced data ? both fields of f1 and f2 ? line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) ? both fields of f1 and f2 ? a line specified by bits 4 to 0 of cps (total 1 line) (see note 3) ? both fields of f1 and f2 ? line 21 (total 1 line) ? both fields of f1 and f2 ? line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) cps b7 0 0 1 1 b6 0 1 0 1 notes 1: dsc1 is data slicer control register 1. cps is caption position register. 2: set 00 16 to 10 16 to bits 4 to 0 of cps. 3: set 00 16 to 1f 16 to bits 4 to 0 of cps. table 8.10.1 specification of data slice line b 7b 6b 5b 4b 3b 2b 1b 0 c a p t i o n p o s i t i o n r e g i s t e r ( c p s ) [ a d d r e s s 0 0 e 6 1 6 ] c a p t i o n p o s i t i o n r e g i s t e r 0 t o 4 0 rw 0r w c a p t i o n p o s i t i o n b i t s ( c p s 0 t o c p s 4 ) 6 , 7r e f e r t o t h e c o r r e s p o n d i n g t a b l e ( t a b l e 8 . 1 0 . 1 ) . s l i c e l i n e m o d e s p e c i f i c a t i o n b i t s ( i n 1 f i e l d ) ( c p s 6 , c p s 7 ) 50 : d a t a i s n o t l a t c h e d y e t a n d a c l o c k - r u n - i n i s n o t d e t e r m i n e d . 1 : d a t a i s l a t c h e d a n d a c l o c k - r u n - i n i s d e t e r m i n e d . c a p t i o n d a t a l a t c h c o m p l e t i o n f l a g 2 ( c p s 5 ) i n d e t e r m i n a t e r b a f t e r r e s e t f u n c t i o n sn a m e rw
56 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.7 reference voltage generating circuit and comparator the composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) reference voltage generating circuit this circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. connect a capacitor between the v hold pin and the v ss pin, and make the length of wiring as short as possible so that a leakage current may not be gener- ated. (2) comparator the comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the refer- ence voltage generating circuit, and converts the composite video signal into a digital value. fig. 8.10.10 clock run-in detect register 8.10.8 start bit detecting circuit this circuit detects a start bit at line decided in the data slice line specification circuit. the detection of a start bit is described below. ? a sampling clock is generated by dividing the reference clock out- put by the timing signal. ? a clock run-in pulse is detected by the sampling clock. ? after detection of the pulse, a start bit pattern is detected from the comparator output. 8.10.9 clock run-in determination circuit this circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. the reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00e4 16 ). read out these bits after the occurrence of a data slicer interrupt (refer to 8.10.12 interrupt request generating circuit). figure 8.10.10 shows the structure of clock run-in detect register. b7 b6 b5 b4 b3 b2 b1 b0 clock run-in detect register (crd) [address 00e4 16 ] r w clock run-in detect register 0 to 2 0r test bits 3 to 7 number of reference clocks to be counted in one clock run-in pulse period. clock run-in detection bit (crd3 to crd7) 0r read-only b after resetfunctionsname
57 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.10 data clock generating circuit this circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. the data clock stores cap- tion data to the 16-bit shift register. when the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. this flag is reset at a falling of the vertical synchronous signal (v sep ). fig. 8.10.11 data clock position register b 7b 6b 5b 4b 3b 2b 1b 0 d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) [ a d d r e s s 0 0 e 5 1 6 ] d a t a c l o c k p o s i t i o n r e g i s t e r 01 rw f i x t h i s b i t t o 0 . 1f i x t h i s b i t t o 1 . 0rw 10 0 b a f t e r r e s e t f u n c t i o n s n a m e rw 3 d a t a c l o c k p o s i t i o n s e t b i t s ( d p s 3 t o d p s 7 ) 1rw 4 t o 7 0 2f i x t h i s b i t t o 0 . 0rw
58 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.10.11 16-bit shift register the caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. the contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00e3 16 ) and data register 4 (address 00cf 16 ). the contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00e2 16 ) and data register 3 (address 00ce 16 ), respectively. these registers are reset to 0 at a falling of v sep . read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to 8.10.12 inter- rupt request generating circuit). 8.10.12 interrupt request generating circuit the interrupt requests as shown in table 8.10.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00e6 16 ). read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request. slice line specification mode cps completion flag 1 (bit 0 of dsc2) completion flag 2 (bit 5 of cps) caption data registers 1, 2 caption data registers 3, 4 line 21 a line specified by bits 4 to 0 of cps line 21 line 21 a line specified by bits 4 to 0 of cps invalid invalid a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps invalid invalid 16-bit data of a line specified by bits 4 to 0 of cps contents of caption data latch completion flag contents of 16-bit shift register bit 7 0 0 1 1 bit 6 0 1 0 1 cps: caption position register dsc2: data slicer control register 2 table 8.10.2 contents of caption data latch completion flag and 16-bit shift register caption position register occurence souces of interrupt request at end of data slice line after slicing line 21 after a line specified by bits 4 to 0 of cps after slicing line 21 after slicing line 21 b7 0 1 b6 0 1 0 1 table 8.10.3 occurence sources of interrupt request
59 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.10.12 sync pulse counter register 8.10.13 synchronous signal counter the synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal v sep as a count source. the count value in a certain time (t time) generated by f(x in )/2 13 or f(x in )/2 13 is stored into the 5-bit latch. accordingly, the latch value changes in the cycle of t time. when the count value exceeds 1f 16 , 1f 16 is stored into the latch. fig. 8.10.13 synchronous signal counter block diagram the latch value can be obtained by reading out the sync pulse counter register (address 00e9 16 ). a count source is selected by bit 5 of the sync pulse counter register. the synchronous signal counter is used when bit 0 of pwm mode register 1 (address 0208 16 ). figure 8.10.12 shows the structure of the sync pulse counter and figure 8.10.13 shows the synchronous signal counter block diagram. b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (hc) [address 00e9 16 ] r w sync pulse counter register 0 to 4 0r 6, 7 0 r count value (hc0 to hc4) 5 0rw count source (hc5) 0: h sync signal 1: composite sync signal b after reset functionsname nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. reset 5-bit counter latch (5 bits) f(x in )/2 13 composite sync signal h sync signal counter sync pulse counter register data bus selection gate : connected to black side when reset. b5
60 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11 osd functions table 8.11.1 outlines the osd functions. this microcomputer incorporates an osd circuit of 32 characters 5 2 lines. and also, there are 2 display modes and they are selected by a block unit. the display modes are selected by bits 0 and 1 of block control register i (i = 1 and 2). the features of each mode are described below. table 8.11.1 features of each display mode number of display characters 32 characters 5 2 lines dot structure 16 5 26 dots (character display area : 16 5 20 dots) 16 5 20 dots kinds of characters 254 kinds kinds of character sizes 1 kinds 8 kinds pre-divide ratio (see note) 5 2 (fixed) 5 2, 5 3 dot size 1t c 5 1/2h 1t c 5 1/2h, 1t c 5 1h, 2t c 5 2h, 3t c 5 3h attribute smooth italic, under line, flash border (black) character font coloring 1 screen : 8 kinds (per character unit) character background coloring 1 screen : 8 kinds (per character unit) osd output r, g, b raster coloring possible (per character unit) function auto solid space function window function display position horizontal: 128 levels, vertical: 512 levels display expansion (multiline display) possible parameter notes 1: the divide ratio of the frequency divider (the pre-divide circuit) is referred as ?re-divide ratio?hereafter. 2: the character size is specified with dot size and pre-divide ratio (refer to 8.11.2 dot size). display mode cc mode (closed caption mode) osd mode (border off) (on-screen display mode)
61 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 16 dots 26 dots 20 dots ? underline area ] ? blank area ] ] : displayed only in ccd mode. ? blank area ] 20 dots osd mode cc mode 16 dots the osd circuit has an extended display mode. this mode allows multiple lines (3 lines or more) to be displayed on the screen by inter- rupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. figure 8.11.1 shows the configuration of osd character. figure 8.11.2 shows the block diagram of the osd circuit. figure 8.11.3 shows the osd control register. figure 8.11.4 shows the block control register i. fig. 8.11.1 configuration of osd character display area
62 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.2 block diagram of osd circuit d i s p l a y o s c i l l a t i o n c i r c u i t o s c 1 o s c 2 h s y n c v s y n c r a m f o r o s d 2 b y t e s 5 3 2 c h a r a c t e r s 5 2 l i n e s d a t a b u s r o m f o r o s d 1 6 d o t s 5 2 0 d o t s 5 2 5 4 c h a r a c t e r s s h i f t r e g i s t e r 1 6 - b i t d a t a s l i c e r c l o c k c l o c k f o r o s d o u t p u t c i r c u i t r g b o s d c o n t r o l c i r c u i t o u t 1 o u t 2 c o n t r o l r e g i s t e r s f o r o s d ( a d d r e s s 0 0 d 0 1 6 ) ( a d d r e s s 0 0 d 1 1 6 ) ( a d d r e s s e s 0 0 d 2 1 6 , 0 0 d 3 1 6 ) ( a d d r e s s e s 0 0 d 4 1 6 , 0 0 d 5 1 6 ) ( a d d r e s s e s 0 0 d 6 1 6 , 0 0 d 7 1 6 ) ( a d d r e s s 0 0 d 8 1 6 ) ( a d d r e s s 0 0 d 9 1 6 ) o s d c o n t r o l r e g i s t e r h o r i z o n t a l p o s i t i o n r e g i s t e r b l o c k c o n t r o l r e g i s t e r i v e r t i c a l p o s i t i o n r e g i s t e r i w i n d o w r e g i s t e r i i / o p o l a r i t y c o n t r o l r e g i s t e r r a s t e r c o l o r r e g i s t e r
63 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.3 osd control register b7 b6 b5 b4 b3 b2 b1 b0 osd control register (oc) [address 00d0 16 ] b name functions after reset r w osd control register 0 osd control bit (oc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 automatic solid space control bit (oc1) 0 : off 1 : on 0 2 0 : off 1 : on 0 0 4 osd mode clock selection bit (oc4) 0 window control bit (oc2) rw rw rw rw rw 3 0 : data slicer clock 1 : clock from osc1 pin cc mode clock selection bit (oc3) 5, 6 osc1 clock selection bit (oc5, oc6) 0 0: 32 khz oscillating 0 1: do not set. 1 0: lc oscillating, ceramic oscillating 1 1: do not set. b6 b5 0 : data slicer clock 1 : clock from osc1 pin 7 fix this bit to ?. 0rw 0rw 0 note: even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync .
64 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.4 block control register i b7 b6 b5 b4 b3 b2 b1 b0 block control register i (bci) (i=1, 2) [addresses 00d2 16 and 00d3 16 ] block control register i 0, 1 display mode selection bits (bci0, bci1) (see note 1) indeterminate 2, 3 dot size selection bits (bci2, bci3) b4 b3 b2 pre-divide ratio dot size 4 pre-divide ratio selection bit (bci4) 5 7 window top/bottom boundary control bit (bci7) notes 1: bit ra3 of osd ram controls out1 output when bit 5 is ?. bit ra3 of osd ram controls out2 output when bit 5 is ?. 2: tc is osd clock cycle divided in pre-divide circuit. 3: h is h sync . out1/out2 output control bit (bci5) (see note 1) 0: out1 output control 1: out2 output control 6 vertical display start position control bit (bci6) bc16: block 1 bc26: block 1 b1 b0 0 0: display off 0 1: cc mode 1 0: osd mode (border off) 1 1: osd mode (border on) 00 01 10 11 00 01 10 11 0 1 5 2 5 3 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h bc17: window top boundary bc27: window bottom boundary b name functions after reset rw rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw
65 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.1 display position the display positions of characters are specified in units called a block. there are 2 blocks, blocks 1 and 2. up to 32 characters can be displayed in each block (refer to 8.11.5 memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display start position in the horizontal direction can be selected for all blocks in common from 128-step display positions in units of 4t osc (t osc = osd oscillation cycle). the display start position in the vertical direction for each block can be selected from 512-step display positions in units of 1 t h ( t h = h sync cycle). blocks are displayed in conformance with the following rules: ? when the display position of block 1 is overlapped with that of block 2 (figure 8.11.5 (b)), the block 1 is displayed on the front. ? when another block display position appears while one block is displayed (figure 8.11.5 (c)), the block with a larger set value as the vertical display start position is displayed. fig. 8.11.5 display position ( h p ) v p 2 b l o c k 1 b l o c k 2 ( a ) e x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d b l o c k 1 ( b ) e x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 ( b l o c k 2 i s n o t d i s p l a y e d ) ( h p ) v p 1 v p 2 ( c ) e x a m p l e w h e n b l o c k 2 o v e r l a p s i n p r o c e s s o f b l o c k 1 b l o c k 1 b l o c k 2 n o t e : v p 1 o r v p 2 i n d i c a t e s t h e v e r t i c a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k 1 o r 2 . v p 1 ( h p ) v p 1 = v p 2
66 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 the vertical display start position is determined by counting the hori- zontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the i/o po- larity control register (address 00d8 16 ). fig. 8.11.6 supplement explanation for display position w h e n b i t s 0 a n d 1 o f t h e i / o p o l a r i t y c o n t r o l r e g i s t e r ( a d d r e s s 0 0 d 8 1 6 ) a r e s e t t o 1 ( n e g a t i v e p o l a r i t y ) v s y n c s i g n a l i n p u t v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r 0 . 2 5 t o 0 . 5 0 [ m s ] ( a t f ( x i n ) = 8 m h z ) p e r i o d o f c o u n t i n g h s y n c s i g n a l ( s e e n o t e 2 ) h s y n c s i g n a l i n p u t n o t c o u n t 12345 n o t e s 1 : t h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f h s y n c s i g n a l a f t e r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r . 2 : d o n o t g e n e r a t e f a l l i n g e d g e o f h s y n c s i g n a l n e a r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r . 3 : t h e p u l s e w i d t h o f v s y n c a n d h s y n c n e e d s 8 m a c h i n e c y c l e s o r m o r e . 8 m a c h i n e c y c l e s o r m o r e 8 m a c h i n e c y c l e s o r m o r e
67 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.7 vertical position register i (i = 1 and 2) the vertical display start position for each block can be set in 512 steps (where each step is 1t h (t h : h sync cycle)) as values 00 16 to ff 16 in vertical position register i (i = 1 and 2) (addresses 00d4 16 and 00d5 16 ) and values 0 or 1 in bit 6 of block control register i (i = 1 and 2) (addresses 00d2 16 and 00d3 16 ). the vertical position registers is shown in figure 8.11.7. b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w vertical position register i vertical position register i (vpi) (i = 1 and 2) [addresses 00d4 16 , 00d5 16 ] b name functions after reset rw inderterminate vertical display start position control bits (vpi0 to vpi7) (see note) vertical display start position = t h 5 (bci6 5 16 2 + n) (n: setting value, t h : h sync cycle, bci6: bit 6 of block control register i) note: set values except ?0 16 to vpi when bci6 is ?.
68 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 the horizontal display start position is common to all blocks, and can be set in 128 steps (where 1 step is 4t osc , t osc being the osd oscillation cycle) as values 00 16 to ff 16 in bits 0 to 6 of the hori- zontal position register (address 00d1 16 ). the horizontal position reg- ister is shown in figure 8.11.8. fig. 8.11.8 horizontal position register notes 1 : 1t c (t c : osd clock cycle divided in pre-divide circuit) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. accordingly, when 2 blocks have different pre-divide ratios, their horizontal dis- play start position will not match. 2 : the horizontal start position is based on the osd clock source cycle selected for each block. accordingly, when 2 blocks have different osd clock source cycles, their horizontal display start position will not match. 3 : when setting 00 16 to the horizontal position register, it needs ap- proximately 62t osc (= t def ) interval from a rising edge (when nega- tive polarity is selected) of h sync signal to the horizontal display start position. fig. 8.11.9 notes on horizontal display start position 4 t o s c 5 n 4 t o s c 5 n h s y n c 1 t c 1 t c 1 t c n o t e 1 n o t e 2 b l o c k 2 ( p r e - d i v i d e r a t i o = 2 , c l o c k s o u r c e = d a t a s l i c e r c l o c k ) b l o c k 3 ( p r e - d i v i d e r a t i o = 3 , c l o c k s o u r c e = d a t a s l i c e r c l o c k ) b l o c k 4 ( p r e - d i v i d e r a t i o = 3 , c l o c k s o u r c e = o s c 1 ) t d e f t d e f n: v a l u e o f h o r i z o n t a l p o s i t i o n r e g i s t e r ( d e c i m a l n o t a t i o n ) 1 t c : o s d c l o c k c y c l e d i v i d e d i n p r e - d i v i d e c i r c u i t t o s c : o s d o s c i l l a t i o n c y c l e t d e f : 6 2 t o s c b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00d1 16 ] b name horizontal position register 7 horizontal display start position control bits (hp0 to hp6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. functions after reset r w horizontal display start positions 128 steps (00 16 to 7f 16 ) (1 step is 4t osc ) 0 0 rw r 0 to 6 note: the setting value synchronizes with the v sync .
69 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.10 block diagram of dot size control circuit 8.11.2 dot size the dot size can be selected by a block unit. the dot size in vertical direction is determined by dividing h sync in the vertical dot size con- trol circuit. the dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (data slicer clock, osc1) in the pre-divide circuit. the clock cycle divided in the pre-divide circuit is defined as 1t c . the dot size of each block is specified by bits 2 to 4 of the block control register i. refer to figure 8.11.4 (the structure of the block control register). the block diagram of dot size control circuit is shown in figure 8.11.10. fig. 8.11.11 definition of dot sizes d a t a s l i c e r c l o c k h s y n c o s c 1 o c 3 o r o c 4 s y n c h r o n o u s c i r c u i t c y c l e 5 3 p r e - d i v i d e c i r c u i t c l o c k c y c l e = 1 t c h o r i z o n t a l d o t s i z e c o n t r o l c i r c u i t v e r t i c a l d o t s i z e c o n t r o l c i r c u i t o s d c o n t r o l c i r c u i t c y c l e 5 2 0 1 b c i 4 n o t e : t o u s e d a t a s l i c e r c l o c k , s e t b i t 0 o f d a t a s l i c e r c o n t r o l r e g i s t e r 1 t o 1 . 1 d o t s c a n n i n g l i n e o f f 1 ( f 2 ) s c a n n i n g l i n e o f f 2 ( f 1 ) 1 / 2 h 1 h 2 h 3 h 3 t c 2 t c 1 t c 1 t c
70 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 of raster color register osd control register i/o port 1 1 0 8.11.3 clock for osd as a clock for display to be used for osd, it is possible to select one of the following 3 types. ? data slicer clock output from the data slicer (approximately 26 mhz) ? osc1 clock supplied from the pins osc1 and osc2 ? clock from the ceramic resonator or the lc oscillator from the pins osc1 and osc2 this osd clock for each block can be selected by the following bits : bit 7 of the raster color register (address 00d9 16 ), bits 3 to 6 of the clock source control register (addresses 00d0 16 ). a variety of char- acter sizes can be obtained by combining dot sizes with osd clocks. when not using the pins osc1 and osc2 for the osd clock i/o pins, the pins can be used as sub-clock i/o pins or port p2. fig. 8.11.12 block diagram of osd selection circuit table 8.11.2 setting for p2 6 /osc1/x cin , p2 7 /osc2/x cout osd clock i/o pin 0 1 0 sub-clock i/o pin 0 0 0 function register b6 b5 0 1 0 0 d a t a s l i c e r c i r c u i t d a t a s l i c e r c l o c k ( s e e n o t e ) o s c 1 c l o c k c e r a m i c l c o s c i l l a t i n g m o d e f o r o s d o c 6 , o c 5 1 1 o c 3 o c 4 c c m o d e b l o c k o s d m o d e b l o c k n o t e : t o u s e d a t a s l i c e r c l o c k , s e t b i t 0 o f d a t a s l i c e r c o n t r o l r e g i s t e r 1 t o 1 .
71 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.4 field determination display to display the block with vertical dot size of 1/2h, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. the dot line 0 or 1 (re- fer to figure 8.11.14) corresponding to the field is displayed alter- nately. in the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. a field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the v sync control signal (refer to figure 8.11.6) in the microcomputer and then comparing this time with the time of the previous field. when the time is longer than the compar- ing time, it is regarded as even field. when the time is shorter, it is regarded as odd field the contents of this field can be read out by the field determination flag (bit 6 of the i/o polarity control register at address 00d8 16 ). a dot line is specified by bit 5 of the i/o polarity control register (refer to figure 8.11.14). however, the field determination flag read out from the cpu is fixed to 0 at even field or 1 at odd field, regardless of bit 5. fig. 8.11.13 i/o polarity control register 0 : ? ?at even field ? ?at odd field 1 : ? ?at even field ? ?at odd field b7 b6 b5 b4 b3 b2 b1 b0 i/o polarity control register (pc) [address 00d8 16 ] b name functions after reset r w i/o polarity control register 0h sync input polarity switch bit (pc0) 0 : positive polarity input 1 : negative polarity input 0 1 0 : positive polarity input 1 : negative polarity input 0 2 r, g, b output polarity switch bit (pc2) 0 : positive polarity output 1 : negative polarity output 0 3 out1 output polarity switch bit (pc3) 0 : positive polarity output 1 : negative polarity output 0 4 out2 output polarity switch bit (pc4) 0 : positive polarity output 1 : negative polarity output 0 5 display dot line selection bit (pc5) (see note) 0 6 field determination flag (pc6) 0 : even field 1 : odd field 1 7 0 v sync input polarity switch bit (pc1) rw rw rw rw rw rw r rw fix this bit to ?. note: refer to the corresponding figure (8.11.14). 0
72 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.14 relation between field determination flag and display font both h sync signal and v sync signal are negative-polarity input field even odd field determination flag(note) display dot line selection bit display dot line 0 (t2 > t1) 1 (t3 < t2) 0 1 0 1 when using the field determination flag, be sure to set bit 0 of the pwm mode register 1 (address 0208 16 ) to ?. t2 t3 osd rom font configuration diagram dot line 0 dot line 1 odd dot line 0 dot line 1 (n | 1) field (odd-numbered) t1 0.25 to 0.50[ s] at f(x in ) 8 mhz cc mode 13579111315 1 3 5 7 9 11 13 15 17 19 21 23 25 26 24 22 20 18 16 14 12 10 8 6 4 2 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 17 19 20 18 16 14 12 10 8 6 4 2 13579111315 2 4 6 8 10 12 14 16 osd mode h sync v sync and v sync control signal in microcom- puter upper : v sync signal lower : v sync control signal in micro- computer (n) field (even-numbered) (n { 1) field (odd-numbered) when the display dot line selection bit is ?, the ? ?font is displayed at even field, the ? ?font is displayed at odd field. bit 6 of the i/o polarity control register can be read as the field determination flag : ??is read at odd field, ??is read at even field. note : the field determination flag changes at a rising edge of the v sync control signal (negative-polarity input) in the microcomputer.
73 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.5 memory for osd there are 2 types of memory for osd : osd rom used to store character dot data and osd ram used to specify the characters and colors to be displayed. osd rom : addresses 1400 16 to 3bff 16 osd ram : addresses 0800 16 to 087f 16 <M37273MF-XXXSP, m37273efsp> osd rom : addresses 11400 16 to 13bff 16 osd ram : addresses 0800 16 to 087f 16 fig. 8.11.15 character font data storing address o s d r o m a d d r e s s o f c h a r a c t e r f o n t d a t a a d 1 5 a d 1 4 a d 1 3 a d 1 2 a d 1 1 a d 1 0 a d 9 a d 8 a d 7 a d 6 a d 5 a d 4 a d 3 a d 2 a d 1a d 0 l i n e n u m b e r c h a r a c t e r c o d e f o n t b i t 0 a 1 6 t o 1 d 1 6 0 0 1 6 t o f f 1 6 ( 7 f 1 6 a n d 8 0 1 6 c a n n o t b e u s e d ) 0 : l e f t a r e a 1 : r i g h t a r e a o s d r o m a d d r e s s b i t l i n e n u m b e r / c h a r a c t e r c o d e / f o n t b i t 0 l i n e n u m b e rc h a r a c t e r c o d e f o n t b i t 0 a0 0 0 0 1 6 7 f f 0 1 6 7 f f 8 1 6 6 0 1 c 1 6 6 0 0 c 1 6 6 0 0 c 1 6 6 0 0 c 1 6 6 0 0 c 1 6 1 1 0 b 0 c 0 d 0 e 0 f 1 0 1 26 0 1 c 1 6 7 f f 8 1 6 7 f f 0 1 6 6 3 0 0 1 6 6 3 8 0 1 6 6 1 c 0 1 6 6 0 e 0 1 6 6 0 7 0 1 6 1 9 1 3 1 4 1 5 1 6 1 7 1 8 6 0 3 8 1 6 6 0 1 c 1 6 6 0 0 c 1 6 0 0 0 0 1 6 1 d 1 a 1 b 1 c b 0 b 7b 0 b 7 l i n e n u m b e r l e f t a r e a r i g h t a r e a d a t a i n o s d r o m c h a r a c t e r f o n t 0 a d 1 6 1 ( n o t e ) n o t e : o n l y m 3 7 2 7 3 m f - x x x s p a n d m 3 7 2 7 3 e f s p h a v e a d 1 6 . (1) osd rom (addresses 1400 16 to 3bff 16 ) the dot pattern data for osd characters is stored in osd rom. to specify the kinds of the character font, it is necessary to write the character code into the osd ram. data of the character font is specified shown in figure 8.11.15.
74 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 notes 1 : the 80-byte addresses corresponding to the character code 7f 16 and 80 16 in osd rom are the test data storing area. set data to the area as follows. n m37273m8-xxxsp, m37273e8sp addresses 1000 16 + (4 + 2n) 5 100 16 + fe 16 to 1000 16 + (5 + 2n) 5 100 16 + 01 16 (n = 0 to 19) n M37273MF-XXXSP, m37273efsp addresses 11000 16 + (4 + 2n) 5 100 16 + fe 16 to 11000 16 + (5 + 2n) 5 100 16 + 01 16 (n = 0 to 19) (1)mask version (m37273m8-xxxsp, m37273e8sp) set ff 16 to the area (we stores the test data to this area and the different data from ff 16 is stored for the actual products.) when using our font editor, the test data is written automatically. (2)eprom version (M37273MF-XXXSP, m37273efsp) set the test data to the area. when using our font editor, the test data is written automatically. ? ? B B B B B B ? ? ? B B B B B B ? 1500 16 (90 16 ), 1501 16 (a1 16 ) 1700 16 (00 16 ), 1701 16 (a2 16 ) 1900 16 (48 16 ), 1901 16 (a3 16 ) 1b00 16 (00 16 ), 1b01 16 (a4 16 ) 1d00 16 (24 16 ), 1d01 16 (a5 16 ) 1f00 16 (00 16 ), 1f01 16 (a6 16 ) 2100 16 (12 16 ), 2101 16 (a7 16 ) 2300 16 (00 16 ), 2301 16 (a8 16 ) 2500 16 (09 16 ), 2501 16 (a9 16 ) 2700 16 (00 16 ), 2701 16 (aa 16 ) 2900 16 (81 16 ), 2901 16 (ab 16 ) 2b00 16 (18 16 ), 2b01 16 (ac 16 ) 2d00 16 (00 16 ), 2d01 16 (ad 16 ) 2f00 16 (42 16 ), 2f01 16 (ae 16 ) 3100 16 (24 16 ), 3101 16 (af 16 ) 3300 16 (00 16 ), 3301 16 (b0 16 ) 3500 16 (81 16 ), 3501 16 (b1 16 ) 3700 16 (0c 16 ), 3701 16 (b2 16 ) 3900 16 (06 16 ), 3901 16 (b3 16 ) 3b00 16 (00 16 ), 3b01 16 (b4 16 ) 11500 16 (90 16 ), 11501 16 (a1 16 ) 11700 16 (00 16 ), 11701 16 (a2 16 ) 11900 16 (48 16 ), 11901 16 (a3 16 ) 11b00 16 (00 16 ), 11b01 16 (a4 16 ) 11d00 16 (24 16 ), 11d01 16 (a5 16 ) 11f00 16 (00 16 ), 11f01 16 (a6 16 ) 12100 16 (12 16 ), 12101 16 (a7 16 ) 12300 16 (00 16 ), 12301 16 (a8 16 ) 12500 16 (09 16 ), 12501 16 (a9 16 ) 12700 16 (00 16 ), 12701 16 (aa 16 ) 12900 16 (81 16 ), 12901 16 (ab 16 ) 12b00 16 (18 16 ), 12b01 16 (ac 16 ) 12d00 16 (00 16 ), 12d01 16 (ad 16 ) 12f00 16 (42 16 ), 12f01 16 (ae 16 ) 13100 16 (24 16 ), 13101 16 (af 16 ) 13300 16 (00 16 ), 13301 16 (b0 16 ) 13500 16 (81 16 ), 13501 16 (b1 16 ) 13700 16 (0c 16 ), 13701 16 (b2 16 ) 13900 16 (06 16 ), 13901 16 (b3 16 ) 13b00 16 (00 16 ), 13b01 16 (b4 16 ) 2 : the character code 09 16 is used for transparent space when displaying closed caption. therefore, set 00 16 to the 40-byte addresses corresponding to the character code 09 16 . n m37273m8-xxxsp, m37273e8sp addresses 1000 16 + (4 + 2n) 5 100 16 + 12 16 to 1000 16 + (4 + 2n) 5 100 16 + 13 16 (n = 0 to 19) addresses 1412 16 and 1413 16 addresses 1612 16 and 1613 16 addresses 3812 16 and 3813 16 addresses 3a12 16 and 3a13 16 n M37273MF-XXXSP, m37273efsp addresses 11000 16 + (4 + 2n) 5 100 16 + 12 16 to 11000 16 + (4 + 2n) 5 100 16 + 13 16 (n = 0 to 19) addresses 11412 16 and 11413 16 addresses 11612 16 and 11613 16 addresses 13812 16 and 13813 16 addresses 13a12 16 and 13a13 16 14fe 16 (09 16 ), 14ff 16 (51 16 ) 16fe 16 (00 16 ), 16ff 16 (52 16 ) 18fe 16 (12 16 ), 18ff 16 (53 16 ) 1afe 16 (00 16 ), 1aff 16 (54 16 ) 1cfe 16 (24 16 ), 1cff 16 (55 16 ) 1efe 16 (00 16 ), 1eff 16 (56 16 ) 20fe 16 (88 16 ), 20ff 16 (57 16 ) 22fe 16 (00 16 ), 22ff 16 (58 16 ) 24fe 16 (90 16 ), 24ff 16 (59 16 ) 26fe 16 (48 16 ), 26ff 16 (5a 16 ) 28fe 16 (24 16 ), 28ff 16 (5b 16 ) 2afe 16 (00 16 ), 2aff 16 (5c 16 ) 2cfe 16 (24 16 ), 2cff 16 (5d 16 ) 2efe 16 (48 16 ), 2eff 16 (5e 16 ) 30fe 16 (00 16 ), 30ff 16 (5f 16 ) 32fe 16 (48 16 ), 32ff 16 (50 16 ) 34fe 16 (90 16 ), 34ff 16 (51 16 ) 36fe 16 (00 16 ), 36ff 16 (52 16 ) 38fe 16 (01 16 ), 38ff 16 (53 16 ) 3afe 16 (80 16 ), 3aff 16 (54 16 ) address (test data) n m37273e8sp <80 16 > address (test data) 114fe 16 (09 16 ), 114ff 16 (51 16 ) 116fe 16 (00 16 ), 116ff 16 (52 16 ) 118fe 16 (12 16 ), 118ff 16 (53 16 ) 11afe 16 (00 16 ), 11aff 16 (54 16 ) 11cfe 16 (24 16 ), 11cff 16 (55 16 ) 11efe 16 (00 16 ), 11eff 16 (56 16 ) 120fe 16 (88 16 ), 120ff 16 (57 16 ) 122fe 16 (00 16 ), 122ff 16 (58 16 ) 124fe 16 (90 16 ), 124ff 16 (59 16 ) 126fe 16 (48 16 ), 126ff 16 (5a 16 ) 128fe 16 (24 16 ), 128ff 16 (5b 16 ) 12afe 16 (00 16 ), 12aff 16 (5c 16 ) 12cfe 16 (24 16 ), 12cff 16 (5d 16 ) 12efe 16 (48 16 ), 12eff 16 (5e 16 ) 130fe 16 (00 16 ), 130ff 16 (5f 16 ) 132fe 16 (48 16 ), 132ff 16 (50 16 ) 134fe 16 (90 16 ), 134ff 16 (51 16 ) 136fe 16 (00 16 ), 136ff 16 (52 16 ) 138fe 16 (01 16 ), 138ff 16 (53 16 ) 13afe 16 (80 16 ), 13aff 16 (54 16 ) <7f 16 > address (test data) n m37273efsp <80 16 > address (test data)
75 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 table 8.11.3 contents of osd ram block character code specification color code specification 31st character 3rd character : 30th character 2nd character 32nd character 31st character 3rd character : 30th character 1st character 2nd character 32nd character 081e 16 0802 16 : 081d 16 0801 16 081f 16 085e 16 0842 16 : 085d 16 0840 16 0841 16 085f 16 083e 16 0822 16 : 083d 16 0821 16 083f 16 087e 16 0862 16 : 087d 16 0860 16 0861 16 087f 16 block 1 display position (from left) block 2 1st character 0800 16 0820 16 (2) osd ram the ram for osd is allocated at addresses 0800 16 to 087f 16 , and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. table 8.11.3 shows the contents of the osd ram. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0800 16 , write the color code 1 at 0820 16 . the structure of the osd ram is shown in figure 8.11.16.
76 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.16 bit structure of osd ram bit name control of character color r control of character color g control of character color b out1/out2 control flash control underline control italic control bit rf0 rf1 rf2 rf3 rf4 rf5 rf6 rf7 ra0 ra1 ra2 ra3 ra4 ra5 ra6 function character code in osd rom 0: color signal output off 1: color signal output on 0: flash off 1: flash on 0: underline off 1: underline on 0: italic off 1: italic on bit name control of character color r control of character color g control of character color b out1/out2 control control of background color r control of background color g control of background color b cc mode function character code in osd rom 0: color signal output off 1: color signal output on 0: color signal output off 1: color signal output on osd mode notes 1: read value of bits 7 of the color code is 0. 2: for out1/out2 control, refer to 8.11.8 out1/out2 signal. 3: 7f 16 and 80 16 cannot be used as character code. character code character code (see note 2) (see note 2) r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r f 7 r f 6 r f 5 r f 4 r f 3 r f 2 r f 1r f 0 b 0b 7b 0b 7 b l o c k s 1 , 2 c h a r a c t e r c o d e ( s e e n o t e 3 )c o l o r c o d e 1 ( s e e n o t e 1 )
77 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.7 character background color the character background color can be displayed in the character display area only in the osd mode. the character background color for each character is specified by the color code. <7 kinds> specified by bits 4 (r), 5 (g), and 6 (b) of the color code note : the character background color is displayed in the following part : (character display area)C(character font)C(border). accordingly, the character background color does not mix with these color signal. 8.11.6 character color the color for each character is displayed by the color code. < 7 kinds> specified by bits 0 (r), 1 (g), and 2 (b) of the color code
78 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.8 out1, out2 signals the out1, out2 signals are used to control the luminance of the video signal. the output waveform of the out1, out2 signals is controlled by display mode, bit 5 of the block control register i (refer to figure 8.11.4) and ra3 of osd ram. the setting values for fig. 8.11.17 setting value for controlling out1, out2 and corresponding output waveform controlling out1, out2 and the corresponding output waveform is shown in figure 8.11.17. note : when out2 signal is output, set bit 7 of osd port control register (refer to figure 8.11.28) to 1. 0 ( o u t 1 o u t p u t i s c o n t r o l l e d b y r a 3 ) 1 o u t 1 = f o n t / b o r d e r d i s p l a y m o d e o u t 1 / o u t 2 o u t p u t c o n t r o l b i t ( b 5 ) o u t 1 / o u t 2 c o n t r o l o u t p u t w a v e f o r m ( a - a ' ) o s d c c 1 ( o u t 2 o u t p u t i s c o n t r o l l e d b y r a 3 ) 0 1 0 1 0 1 0 o u t 2 = l o u t 1 = a r e a o u t 2 = l o u t 1 = f o n t / b o r d e r o u t 2 = l o u t 1 = f o n t / b o r d e r o u t 2 = a r e a o u t 1 = f o n t o u t 2 = l o u t 1 = a r e a o u t 2 = l o u t 1 = f o n t o u t 2 = l o u t 1 = f o n t o u t 2 = a r e a a a ' 0 ( o u t 1 o u t p u t i s c o n t r o l l e d b y r a 3 ) 1 ( o u t 2 o u t p u t i s c o n t r o l l e d b y r a 3 ) n o t e s1 : f o n t / b o r d e r . . . . . i n t h e o s d m o d e ( b o r d e r o n ) , o u t 1 o u t p u t s t o t h e a r e a o f f o n t a n d b o r d e r . i n t h e o s d m o d e ( b o r d e r o f f ) , o u t 1 o u t p u t s t o o n l y t h e f o n t a r e a . a r e a . . . . . . . . . . . . . . . . . . . . .o u t 1 / o u t 2 o u t p u t s t o e n t i r e d i s p l a y a r e a o f c h a r a c t e r . f o n t . . . . . . . . . . . . . . . . . . . . .i n t h e c c m o d e , o u t 1 o u t p u t s t o f o n t a r e a . 2 : w h e n t h e a u t o m a t i c s o l i d s p a c e f u n c t i o n i s o f f i n t h e c c m o d e , a r e a o u t p u t s a c c o r d i n g t o b i t 3 o f c o l o r c o d e . w h e n i t i s o n , t h e s o l i d s p a c e i s a u t o m a t i c a l l y o u t p u t b y a c h a r a c t e r c o d e r e g a r d l e s s o f r a 3 . b l o c k c o n t r o l r e g i s t e r i r a 3 o f o s d r a m
79 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.9 attribute the attributes (border, flash, underline, italic) are controlled to the character font. the attributes to be controlled are different depend- ing on each mode. cc mode ..................... flash, underline, italic (per character unit) osd mode .................. border (per character unit) (1) under line the underline is output at the 23th and 24th dots in vertical direction only in the cc mode. the underline is controlled by ra5 of osd ram. the color of underline is the same color as that of the charac- ter font. (2) flash the character font and the underline are flashed only in the cc mode. the flash is controlled by ra4 of osd ram. as for character font part, the character output part is flashed, the character background part is not flashed. the flash cycle bases on the v sync count. ? v sync cycle 5 48 a 800 ms (at display on) ? v sync cycle 5 16 a 267 ms (at display off) (3) italic the italic is made by slanting the font stored in osd rom to the right only in the cc mode. the italic is controlled by ra6 of osd ram. the display example of the italic and underline is shown in figure 8.11.8. in this case, r is displayed. notes 1: when setting both the italic and the flash, the italic character flashes. 2: the boundary of character color is displayed in italic. however, the boundary of character background color is not affected by the italic (refer to figure 8.11.19). 3: the adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to figure 8.11.19).
80 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.18 example of attribute display (in cc mode) c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 00 c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 01 c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 01 c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 10 ( a ) o r d i n a r y( b ) u n d e r l i n e ( c ) i t a l i c ( p r e - d i v i d e r a t i o = 1 )( d ) i t a l i c ( p r e - d i v i d e r a t i o = 2 ) f l a s hf l a s hf l a s h o f fo f f o no n c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) b i t 6 ( r a 6 ) 111 ( e ) u n d e r l i n e a m d i t a l i c a n d f l a s h
81 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.19 example of italic display 10 0 1 1 0 1 ( r e f e r t o 8 . 1 1 . 9 n o t e s 2 , 3 )( r e f e r t o 8 . 1 1 . 9 n o t e s 2 , 3 ) r a 6 o f o s d r a m n o t e s 1 : t h e d o t t e d l i n e i s t h e b o u n d a r y o f c h a r a c t e r c o l o r . 2 : w h e n b i t 1 o f o s d c o n t r o l r e g i s t e r i s 0 . 2 6 t h c h r a c t e r
82 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 (4) border the border is output around of character font (all bordered) in the osd mode. the border on/off is controlled by bit 0 and 1 of the block control register i (refer to figure 8.11.4). the out1 signal is used for border output. the horizontal size (x) of border is 1t c (osd clock cycle divided in pre-divide circuit) regardless of the character font dot size. the verti- cal size (y) different depending on the screen scan mode and the vertical dot size of character font. notes 1 : the border dot area is the shaded area as shown in figure 8.11.20. 2 : when the border dot overlaps on the next character font, the charac- ter font has priority (refer to figure 8.11.22 a). when the border dot overlaps on the next character back ground, the border has priority (refer to figure 8.11.22 b). 3 : the border in vertical out of character area is not displayed (refer to figure 8.11.22). fig. 8.11.20 example of border display fig. 8.11.21 horizontal and vertical size of border a l l b o r d e r e d 1 6 d o t s 2 0 d o t s o s d m o d e 1 d o t w i d t h o f b o r d e r 1 d o t w i d t h o f b o r d e r c h a r a c t e r f o n t a r e a y x 1 / 2 h 1 h , 2 h , 3 h 1 / 2 h 1 h v e r t i c a l d o t s i z e o f c h a r a c t e r f o n t b o r d e r d o t s i z e h o r i z o n t a l s i z e ( x ) v e r t i c a l s i z e ( y ) 1 t c ( o s d c l o c k c y c l e d i v i d e d i n p r e - d i v i d e c i r c u i t )
83 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.22 border priority character boundary b character boundary a character boundary b
84 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.10 multiline display this microcomputer can ordinarily display 2 lines on the crt screen by displaying 2 blocks at different vertical positions. in addition, it can display up to 16 lines by using osd interrupts. an osd interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. notes 1: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the block control register (addresses 00d2 16 , 00d3 16 ), an osd interrupt request does not occur (refer to figure 8.11.23 (a)). 2: when another block display appeares while one block is displayed, an osd interrupt request occurs only once at the end of the another block display (refer to figure 8.11.23 (b)). 3: on the screen setting window, an osd interrupt occurs even at the end of the cc mode block (off display) out of window (refer to figure 8.11.23 (c)). fig. 8.11.23 note on occurence of osd interrupt (b) (c) block 1 (on display) block 2 (on display) block 1?(on display) block 2?(on display) block 1 (on display) block 2 (on display) block 1?(off display) block 2?(off display) ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request no ?sd interrupt request block 1 block 2 ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request block 1 block 2 block 1 on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) in cc mode window no ?sd interrupt request no ?sd interrupt request (a)
85 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 notes : the character code 09 16 is used for transparent space when dis- playing closed caption. therefore, set 00 16 to the 40-byte addresses corresponding to the character code 09 16 . n m37273m8-xxxsp, m37273e8sp addresses 1000 16 + (4 + 2n) 5 100 16 + 12 16 to 1000 16 + (4 + 2n) 5 100 16 + 13 16 (n = 0 to 19) addresses 1412 16 and 1413 16 addresses 1612 16 and 1613 16 addresses 3812 16 and 3813 16 addresses 3a12 16 and 3a13 16 n M37273MF-XXXSP, m37273efsp addresses 11000 16 + (4 + 2n) 5 100 16 + 12 16 to 11000 16 + (4 + 2n) 5 100 16 + 13 16 (n = 0 to 19) addresses 11412 16 and 11413 16 addresses 11612 16 and 11613 16 addresses 13812 16 and 13813 16 addresses 13a12 16 and 13a13 16 ? 8.11.11 automatic solid space function this function generates automatically the solid space (out1 or out2 blank output) of the character area in the cc mode. the solid space is output in the following area : ? any character area except character code 09 16 ? character area on the left and right sides of the above character this function is turned on and off by bit 1 of the osd control register (refer to figure 8.11.3). fig. 8.11.24 display screen example of automatic solid space ? B B B B B B ? 0 50 90 90 90 60 6 1 61 61 61 61 61 6 0 60 9 1 61 6 0 9 1 6 0 6 1 6 w h e n s e t t i n g t h e c h a r a c t e r c o d e 0 5 1 6 a s t h e c h a r a c t e r a , 0 6 1 6 a s t h e c h a r a c t e r b . ( o s d r a m ) ( d i s p l a y s c r e e n ) 1 s t c h a r a c t e r 2 n d c h a r a c t e r n o b l a n k o u t p u t 3 1 s t c h a r a c t e r 3 2 n d c h a r a c t e r t h e s o l i d s p a c e i s a u t o m a t i c a l l y o u t p u t o n t h e l e f t s i d e o f t h e 1 s t c h a r a c t e r a n d o n t h e r i g h t s i d e o f t h e 3 2 n d c h a r a c t e r b y s e t t i n g t h e 1 s t a n d 3 2 n d o f t h e c h a r a c t e r c o d e . ? B B B B B B ?
86 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.12 window function this function sets the top and bottom boundary of display limit on a screen. the window function is valid only in the cc mode. the top boundary is set by the window registers 1 and bit 7 of block control register 1. the bottom boundary is set by window registers 1 and bit 7 of block control register 2. this function is turned on and off by bit 2 of the osd control register (refer to figure 8.11.3). the window registers 1 and 2 is shown in figures 8.11.26 and 8.11.27. fig. 8.11.25 example of window function osd mode window fgh ij cc mode kl mno cc mode pqrst cc mode osd mode bottom boundary of window top boundary of window screen abcde uvwxy
87 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.26 window register 1 fig. 8.11.27 window register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 1 window register 1 (wn1) [address 00d6 16 ] b name functions after reset rw inderterminate window top boundary control bits (wn10 to wn17) window top border position = t h 5 (bc17 5 16 2 + n) (n: setting value, t h : h sync cycle, bc17: bit 7 of block control register 1) notes 1: set values except ?0 16 ?to wn1 when bc17 is ?. 2: set values fit for the following condition: wn1 < wn2. b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 2 window register 2 (wn2) [address 00d7 16 ] b name functions after reset rw inderterminate window bottom boundary control bits (wn20 to wn27) window bottom border position = t h 5 (bc27 5 16 2 + n) (n: setting value, t h : h sync cycle, bc27: bit 7 of block control register 2) note: set values fit for the following condition: wn1 < wn2.
88 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.13 osd output pin control the osd output pins r, g, b and out1 can also function as ports p5 2 Cp5 5 . set corresponding bit of the osd port control register (ad- dress 00cb 16 ) to 0 to specify these pins as osd output pins, or set it to 1 to specify it as a general-purpose port p5. the out2 can also function as port p1 0 . set bit 0 of the port p1 direction register (address 00c3 16 ) to 1 (output mode). after that, set bit 7 of the osd port control register to 1 to specify the pin as osd output pin, or set it to 0 to specify as port p1 0 . the input polarity of the h sync , v sync and output polarity of signals r, g, b, out1 and out2 can be specified with the i/o polarity con- trol register (address 00d8) . set a bit to 0 to specify positive polar- ity; set it to 1 to specify negative polarity (refer to figure 8.11.13). the structure of the osd port control register is shown in figure 8.11.28. fig. 8.11.28 osd port control register b 7b 6b 5b 4b 3b 2b 1b 0 o s d p o r t c o n t r o l r e g i s t e r ( p f ) [ a d d r e s s 0 0 c b 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w o s d p o r t c o n t r o l r e g i s t e r 0 2 0 30 : g s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t 0 0 f i x t h e s e b i t s t o 0 . r rw rw rw 0 , 1 p o r t p 5 3 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 3 ) 4 0 : b s i g n a l o u t p u t 1 : p o r t p 5 4 o u t p u t 0rw p o r t p 5 4 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 4 ) 0rw 0 : r s i g n a l o u t p u t 1 : p o r t p 5 2 o u t p u t p o r t p 5 2 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 2 ) 5 0 : o u t 1 s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t p o r t p 5 5 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 5 ) 70 : p o r t p 1 0 o u t p u t 1 : o u t 2 s i g n a l o u t p u t p o r t p 1 0 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 7 ) 00 0 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . r 6
89 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.11.14 raster coloring function an entire screen (raster) can be colored by setting the bits 4 to 0 of the raster color register. since each of the r, g, b, out1, and out2 pins can be switched to raster coloring output, 8 raster colors can be obtained. when the character color/the character background color overlaps with the raster color, the color (r, g, b, out1, out2), specified for the character color/the character background color, takes priority of the raster color. this ensures that character color/character back- ground color is not mixed with the raster color. the raster color register is shown in figure 8.11.29, the example of raster coloring is shown in figure 8.11.30. fig. 8.11.29 raster color register b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 00d9 16 ] b name functions after reset r w raster color register 0 raster color r control bit (rc0) 0 : no output 1 : output 0 1 raster color g control bit (rc1) 0 : no output 1 : output 0 2 0 : no output 1 : output 0 0 4 raster color out2 control bit (rc4) 0 raster color b control bit (rc2) rw rw rw rw rw 3 0 : no output 1 : output raster color out1 control bit (rc3) 5, 6 0 : no output 1 : output 7 fix these bits to ?. 0rw 0rw 0 note: either osd clock source or 32 khz oscillating clock is selected by bits 5 and 6 of the osd control register. 0 port function selection bit (rc7) 0 : osc1/x cin , osc2/x cout 1 : p2 6 , p2 7
90 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig. 8.11.30 example of raster coloring h s y n c a ' a o u t 1 r g b : c h a r a c t e r c o l o r r e d ( r + o u t 1 + o u t 2 ) : b o r d e r c o l o r b l a c k ( o u t 1 + o u t 2 ) : b a c k g r o u n d c o l o r m a g e n t a ( r + b + o u t 1 + o u t 2 ) : r a s t e r c o l o r b l u e ( b + o u t 1 + o u t 2 ) s i g n a l s a c r o s s a - a ' o u t 2
91 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig.8.12.1 sequence at detecting software runaway detection 8.12 software runaway detect function this microcomputer has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation, the following processing is done. the cpu generates an undefined instruction decoding signal. the device is internally reset because of occurrence of the unde- fined instruction decoding signal. a as a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. note, however, that the software runaway detecting function cannot be invalid. a d h , a d l 0 1 , s 20 1 , s 1 p c h p c l p sa d h a d l p c ? ? : u n d e f i n e d i n s t r u c t i o n d e c o d e ? u n d e f i n e d i n s t r u c t i o n d e c o d i n g s i g n a l o c c u r s . i n t e r n a l r e s e t s i g n a l o c c u r s . f s y n c a d d r e s s d a t a r e s e t s e q u e n c e 0 1 , sf f f e 1 6 f f f f 1 6 : i n v a l i d : p r o g r a m c o u n t e r s : s t a c k p o i n t e r p c a d l , a d h : j u m p d e s t i n a t i o n a d d r e s s o f r e s e t
92 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.13. reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the reset pin at low for 2 m s or more, then return is to high. then, as shown in figure 8.13.2, reset is released and the program starts form the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal state of microcomputer at reset are shown in figures 8.2.3 to 8.2.6. an example of the reset circuit is shown in figure 8.13.1. the reset input voltage must be kept 0.9 v or less until the power source voltage surpasses 4.5 v. fig.8.13.2 reset sequence fig.8.13.1 example of reset circuit p o w e r s o u r c e v o l t a g e 0 v r e s e t i n p u t v o l t a g e 0 v 4 . 5 v 0 . 9 v p o w e r o n v c c r e s e t v s s m i c r o c o m p u t e r 1 5 4 3 0 . 1 m f m 5 1 9 5 3 a l x i n f r e s e t i n t e r n a l r e s e t s y n c a d d r e s s d a t a 3 2 7 6 8 c o u n t o f x i n c l o c k c y c l e ( s e e n o t e 3 ) r e s e t a d d r e s s f r o m t h e v e c t o r t a b l e ? ? 0 1 , s 0 1 , s - 1 0 1 , s - 2 f f f e f f f f a d h , a d l ? ? ? ? ? a d l a d h n o t e s 1 : f ( x i n ) a n d f ( f ) a r e i n t h e r e l a t i o n : f ( x i n ) = 2 f ( f ) . 2 : a q u e s t i o n m a r k ( ? ) i n d i c a t e s a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e . 3 : i m m e d i a t e l y a f t e r a r e s e t , t i m e r 3 a n d t i m e r 4 a r e c o n n e c t e d b y h a r d w a r e . a t t h i s t i m e , f f 1 6 i s s e t i n t i m e r 3 a n d 0 7 1 6 i s s e t t o t i m e r 4 . t i m e r 3 c o u n t s d o w n w i t h f ( x i n ) / 1 6 , a n d r e s e t s t a t e i s r e l e a s e d b y t h e t i m e r 4 o v e r f l o w s i g n a l .
93 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 8.14 clock generating circuit this microcomputer has 2 built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no external re- sistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . when using x cin -x cout as sub-clock, clear bits 5 and 6 of the osd control register to 0. to supply a clock signal externally, input it to the x in (x cin ) pin and make the x out (x cout ) pin open. when not using x cin clock, connect the x cin to v ss and make the x cout pin open. after reset has completed, the internal clock f is half the frequency of x in . immediately after poweron, both the x in and x cin clock start oscillating. to set the internal clock f to low-speed operation mode, set bit 7 of the cpu mode register to 1. 8.14.1 oscillation control (1) stop mode the built-in clock generating circuit is shown in figure 120. when the stp instruction is executed, the internal clock f stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in timer 4. select f(x in )/16 or f(x cin )/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00c7 16 to 0 before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before execution of the stp instruction. the oscillator restarts when external interrupt is accepted. however, the internal clock f keeps its high level until timer 4 overflows, al- lowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. (2) wait mode when the wit instruction is executed, the internal clock f stops in the high level but the oscillator continues running. this wait state is released at reset or when an interrupt is accepted (see note). since the oscillator does not stop, the next instruction can be executed at once. note: in the wait mode, the following interrupts are invalid. ? v sync interrupt ? osd interrupt ? all timer interrupts using external clock input from port pin as count source ? all timer interrupts using f(x in )/2 or f(x cin )/2 as count source ? all timer interrupts using f(x in )/4096 or f(x cin )/4096 as count source ? f(x in )/4096 interrupt ? multi-master i 2 c-bus interface interrupt ? data slicer interrupt ? a-d conversion interrupt fig.8.14.1 ceramic resonator circuit example fig.8.14.2 external clock input circuit example (3) low-speed mode if the internal clock is generated from the sub-clock (x cin ), a low power consumption operation can be realized by stopping only the main clock x in . to stop the main clock, set bit 6 (cm6) of the cpu mode register (00fb 16 ) to 1. when the main clock x in is restarted, the program must allow enough time to for oscillation to stabilize. note that in low-power-consumption mode the x cin -x cout drivability can be reduced, allowing even lower power consumption. to reduce the x cin -x cout drivability, clear bit 5 (cm5) of the cpu mode regis- ter (00fb 16 ) to 0. at reset, this bit is set to 1 and strong drivability is selected to help the oscillation to start. when an stp instruction is executed, set this bit to 1 by software before executing. x c i n x i n c c i n m i c r o c o m p u t e r x c o u t r f r d c c o u t x o u t c i n c o u t x c i n m i c r o c o m p u t e r e x t e r n a l o s c i l l a t i o n c i r c u i t o r e x t e r n a l p u l s e x c o u t x i n x o u t o p e no p e n e x t e r n a l o s c i l l a t i o n c i r c u i t v c c v s s v c c v s s
94 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig.8.14.3 clock generating circuit block diagram x c i n x c o u t o s c 1 c l o c k s e l e c t i o n b i t s ( s e e n o t e s 1 , 4 ) i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( s e e n o t e s 1 , 3 ) i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( s e e n o t e s 1 , 3 ) m a i n c l o c k ( x i n x o u t ) s t o p b i t ( s e e n o t e s 1 , 3 ) r sq s t p i n s t r u c t i o n w i t i n s t r u c t i o n r s q r e s e t i n t e r r u p t d i s a b l e f l a g i i n t e r r u p t r e q u e s t r s q r e s e t s t p i n s t r u c t i o n t i m i n g f ( i n t e r n a l c l o c k ) t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t ( s e e n o t e s 1 , 2 ) 1 t i m e r 3 c o u n t s t o p b i t ( s e e n o t e s 1 , 2 ) t i m e r 4 c o u n t s t o p b i t ( s e e n o t e s 1 , 2 ) t i m e r 3t i m e r 4 1 / 2 1 / 8 x o u t x i n 1 0 0 n o t e s 1 : t h e v a l u e a t r e s e t i s 0 . 2 : r e f e r t o t i m e r m o d e r e g i s t e r 2 . 3 : r e f e r t o t h e c p u m o d e r e g i s t e r . 4 : r e f e r t o t h e o s d c o n t r o l r e g i s t e r .
95 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig.8.14.4 state transitions of system clock r e s e t t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . t h e f i n d i c a t e s t h e i n t e r n a l c l o c k . w i t i n s t r u c t i o n c m 7 : i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t 0 : x i n - x o u t s e l e c t e d ( h i g h - s p e e d m o d e ) 1 : x c i n - x c o u t s e l e c t e d ( l o w - s p e e d m o d e ) c p u m o d e r e g i s t e r ( a d d r e s s : 0 0 f b 1 6 ) c m 6 : m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d 8 m h z o s c i l l a t i n g 3 2 k h z o s c i l l a t i n g f i s s t o p p e d ( h ) t i m e r o p e r a t i n g 8 m h z o s c i l l a t i n g 3 2 k h z o s c i l l a t i n g f ( f ) = 4 m h z 8 m h z s t o p p e d 3 2 k h z s t o p p e d f i s s t o p p e d ( h ) 8 m h z o s c i l l a t i n g 3 2 k h z o s c i l l a t i n g f i s s t o p p e d ( h ) t i m e r o p e r a t i n g ( s e e n o t e 3 ) 8 m h z o s c i l l a t i n g 3 2 k h z o s c i l l a t i n g f ( f ) = 1 6 k h z 8 m h z s t o p p e d 3 2 k h z s t o p p e d f i s s t o p p e d ( h ) 8 m h z s t o p p e d 3 2 k h z s t o p p e d f = s t o p p e d ( h ) 8 m h z s t o p p e d 3 2 k h z o s c i l l a t i n g f ( f ) = 1 6 k h z 8 m h z s t o p p e d 3 2 k h z o s c i l l a t i n g f i s s t o p p e d ( h ) t i m e r o p e r a t i n g ( s e e n o t e 3 ) i n t e r r u p t s t p i n s t r u c t i o n i n t e r r u p t ( s e e n o t e 1 ) w i t i n s t r u c t i o n i n t e r r u p t w i t i n s t r u c t i o n i n t e r r u p t s t p i n s t r u c t i o n i n t e r r u p t ( s e e n o t e 2 ) s t p i n s t r u c t i o n i n t e r r u p t ( s e e n o t e 2 ) c m 7 = 1 c m 7 = 0 c m 6 = 1 c m 6 = 0 e x t e r n a l i n t , t i m e r i n t e r r u p t , o r s i / o i n t e r r u p t e x t e r n a l i n t n o t e s 1 : w h e n t h e s t p s t a t e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 8 m s i s a u t o m a t i c a l l y g e n e r a t e d b y t i m e r 3 a n d t i m e r 4 . 2 : t h e d e l a y a f t e r t h e s t p s t a t e e n d s i s a p p r o x i m a t e l y 2 s . 3 : w h e n t h e i n t e r n a l c l o c k f d i v i d e d b y 8 i s u s e d a s t h e t i m e r c o u n t s o u r c e , t h e f r e q u e n c y o f t h e c o u n t s o u r c e i s 2 k h z . t h e p r o g r a m m u s t a l l o w t i m e f o r 8 m h z o s c i l l a t i o n t o s t a b i l i z e h i g h - s p e e d o p e r a t i o n s t a r t m o d e
96 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 reset vss vcc circuit example 1 reset vss vcc circuit example 2 note : make the level change from ??to ??at the point at which the power source voltage exceeds the specified voltage. 8.15 display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation circuit is selected by setting bits 5 and 6 of the osd control register (address 00d0 16 ). 8.17 addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 users manual for details. 8.18 machine instructions there are 71 machine instructions. refer to series 740 users manual for details. 9. programming notes ? the divide ratio of the timer is 1/(n+1). ? even though the bbc and bbs instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. at least one instruction cycle is needed (such as an nop) between the modification of the interrupt request bits and the execution of the bbc and bbs instructions. ? after the adc and sbc instructions are executed (in the decimal mode), one instruction cycle (such as an nop) is needed before the sec, clc, or cld instruction is executed. ? an nop instruction is needed immediately after the execution of a plp instruction. ? in order to avoid noise and latch-up, connect a bypass capacitor ( a 0.1 m f) directly between the v cc pinCv ss pin, av cc pinCv ss pin, and the v cc pinCcnv ss pin, using a thick wire. fig.8.15.1 display oscillation circuit 8.16 auto-clear circuit when a power source is supplied, the auto-clear function will oper- ate by connecting the following circuit to the reset pin. fig.8.16.1 auto-clear circuit example osc2osc1 l c1 c2
97 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 symbol parametear 10. absolute maximum ratings 11. recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) ratings C0.3 to 6 C0.3 to 6 C0.3Cv cc + 0.3 C0.3Cv cc + 0.3 C0.3 to 13 0 to 1 (see note 1) 0 to 2 (see note 2) 0 to 6 (see note 2) 0 to 1 (see note 2) 0 to 10 (see note 3) 550 C10 to 70 C40 to 125 parametear power source voltage v cc , av cc input voltage cnv ss input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , ______ p3 1 , p5 0 , p5 1 , x in , reset, cv in output voltage p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p5 2 Cp5 7 , p6 0 Cp6 7 , x out output voltage p0 0 Cp0 5 circuit current p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 p5 2 Cp5 7 , p6 0 Cp6 7 circuit current p0 6 , p0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p2 6 , p2 7 , p5 2 Cp5 7 , p6 0 Cp6 7 circuit current p1 1 Cp1 4 circuit current p0 0 Cp0 5 circuit current p2 4 , p2 5 , p3 0 , p3 1 power dissipation operating temperature storage temperature conditions all voltages are based on v ss . output transistors are cut off. t a = 25 c unit v v v v v ma ma ma ma ma mw c c symbol v cc , av cc v i v i v o v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg min. 4.5 0 0.8 v cc 0.7 v cc 0 0 0 typ. 5.0 0 max. 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 6 1 10 8.1 35 27.0 100 1 400 16.206 2.5 limits v cc , av cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 i ol4 f(x in ) f(x cin ) f osc f hs1 f hs2 f hs3 f hs4 v i power source voltage (see note 4) power source voltage high input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p5 0 , p5 1 , ______ reset, x in high input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) low input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) low input voltage (see note 6) ______ p5 0 , p5 1 , reset, x in , osc1, tim2, tim3, int1, int2, int3, s in , s clk high average output current (see note1) p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p5 2 Cp5 7 , p6 0 Cp6 7 low average output current (see note 2) p0 6 , p0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p2 6 , p2 7 , p5 2 Cp5 7 , p6 0 Cp6 7 low average output current (see note 2) p1 1 Cp1 4 low average output current (see note 2) p0 0 Cp0 5 low average output current (see note 3) p2 4 , p2 5 , p3 0 , p3 1 oscillation frequency (for cpu operation) (see note 5) x in oscillation frequency (for sub-clock operation) x cin oscillation frequency (for osd) osc1 input frequency tim2, tim3, int1, int2, int3 input frequency s clk input frequency scl1, scl2 input frequency horizontal sync. signal of video signal input amplitude video signal cv in v v v v v v v ma ma ma ma ma mhz khz mhz khz mhz khz khz v unit 8.0 32 27.0 15.734 2.0 7.9 29 26.5 15.262 1.5
98 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 max. 30 45 200 4 100 10 0.4 3.0 0.4 0.6 1.3 5 5 10 130 v cc = 5.5v, f(x in ) = 8mhz v cc = 5.5v, f(x in ) = 0, f(x cin ) = 32khz, osd off, data slicer off, low-power dissipation mode set (cm5 = 0, cm6 = 1) v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32 khz, low-power dissipation mode set (cm5 = 0, cm6 = 1) v cc = 5.5v, f(x in ) = 0, f(x cin ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v i = 12 v v cc = 4.5 v 12. electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) notes 1: the total current that flows out of the ic must be 20 ma or less. 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 30 ma or less. 3: the total average input current for ports p3 0 , p3 1 , p2 4 and p2 5 and av cc Cv ss to ic must be 20 ma or less. 4: connect 0.1 m f or more capacitor externally between the power source pins v cc Cv ss and av cc Cv ss so as to reduce power source noise. also connect 0.1 m f or more capacitor externally between the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p0 6 , p0 7 , p1 5 , p2 3 , p2 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 Cp1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p2 0 Cp2 2 have the hysteresis when these pins are used as serial i/o pins. 7: pin names in each parameter is described as below. (1) dedicated pins: dedicated pin names. (2) duble-/triple-function ports ? when the same limits: i/o port name. ? when the limits of functins except ports are different from i/o port limits: function pin name. high output voltage p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p5 2 Cp5 7 , p6 0 Cp6 7 low output voltage p0 0 Cp0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p2 6 , p2 7 , p5 2 Cp5 7 , p6 0 Cp6 7 low output voltage p2 4 , p2 5 , p3 0 , p3 1 low output voltage p1 1 Cp1 4 hysteresis (see note 6) ____________ reset, p5 0 , p5 1 , int1, int2, int3, tim2, tim3, s in , s clk , scl1, scl2, sda1, sda2 high input leak current p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , ____________ p3 0 , p3 1 , reset, p5 0 , p5 1 , high input leak current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , ____________ p3 1 , p5 0 , p5 1 , reset high output leak current p0 0 Cp0 5 i 2 c-bus ? bus switch connection resistor (between scl1 and scl2, sda1 and sda2) i cc symbol parametear test conditions osd off data slicer off osd on data slicer on stop mode wait mode system operation power source current v oh v ol v t+ C v t C i izh i izl i ozh r bs test circuit 1 min. 2.4 limits i ol = 3 ma i ol = 6 ma typ. 15 30 60 2 25 1 0.5 2 3 4 5 6 4 unit ma m a ma m a v v v m a m a m a w 2
99 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 fig.12.1 measure circuits 1 3 5 2 4 6 v s s v c c v v o h o r v o l i o h o r i o l 4 . 5 v e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n t o h i g h l e v e l w h e n m e a s u r i n g v o h a n d t o l o w l e v e l w h e n m e a s u r i n g v o l , e a c h p i n i s m e a s u r e d . v s s v c c 5 . 0 v e a c h i n p u t p i n v s s v c c v b s 4 . 5 v s c l 1 o r s d a 1 i b s a r b s = v b s / i b s s c l 2 o r s d a 2 r b s v s s v c c 5 . 5 v e a c h i n p u t p i n a i i z h o r i i z l v s s v c c 5 . 5 v a e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n o f f s t a t e , e a c h p i n i s m e a s u r e d i oz h 1 2 v a v s s v c c x i n x o u t o s c 1 o s c 2 i c c 8 . 0 0 m h z + p o w e r s o u r c e v o l t a g e p i n v c c i s m a d e t h e o p e r a t i o n s t a t e a n d i s m e a s u r e d t h e c u r r e n t , w i t h a c e r a m i c r e s o n a t o r .
100 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 13. a-d converter characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) resolution non-linearity error differencial non-linearity error zero transition error full-scale transition error max. 6 1 0.9 2 C2 bits lsb lsb lsb lsb min. limits unit test conditions parameter symbol v 0t v fst i ol (sum) = 0 ma typ. 14. multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd; sta t low t r t hd; dat t high t f t su; dat t su; sta t su; sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 m s m s m s ns m s m s ns ns m s m s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig.14.1 definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 s d a s c l p t b u f s t h d ; s t a t l o w t r t h d ; d a t t h i g h t f t s u ; d a t t s u ; s t a s r p t s u ; s t o t h d ; s t a s s r p : s t a r t c o n d i t i o n : r e s t a r t c o n d i t i o n : s t o p c o n d i t i o n
101 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 name of programming adapter pca7426g02 pca7426g02 15. prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. product m37273e8sp m37273efsp the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 15.1 is recommended to verify programming. fig. 15.1 programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150? exceeding 100 hours.
102 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 16. data required for mask orders the following are necessary when ordering a mask rom produc- tion: ? mask rom order confirmation form ? mark specification form ? data to be written to rom, in eprom form (three identical copies) or fdk when using eprom: 28-pin dip type 27512 <M37273MF-XXXSP, m37273efsp> 32-pin dip type 27c101
103 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 17. mask confirmation form gzzCsh55C39b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37273m8-xxxsp mitsubishi electric mask rom number receipt date: section head signature supervisor signature ] customer company name tel ( ) date : date issued issuance signature note : please fill in all items marked ] . submitted by supervisor ] 1. confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) (1) set ff 16 in the shaded area. 1/3 eprom address product nameascii code: 'm37273m8-' 2 7 5 1 2 0000 16 000f 16 12345678901234567 1 234567890123456 7 12345678901234567 osdrom data rom (32k) 1400 16 3bff 16 12345678901234567 1 234567890123456 7 1 234567890123456 7 12345678901234567 8000 16 ffff 16
104 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 gzzCsh55C39b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37273m8-xxxsp mitsubishi electric note : if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. please make sure the data is written correctly. address 0000 16 m = 4d 16 0001 16 3 = 33 16 0002 16 7 = 37 16 0003 16 2 = 32 16 0004 16 7 = 37 16 0005 16 3 = 33 16 0006 16 m = 4d 16 0007 16 8 = 38 16 address 0008 16 C = 2d 16 0009 16 ff 16 000a 16 ff 16 000b 16 ff 16 000c 16 ff 16 000d 16 ff 16 000e 16 ff 16 000f 16 ff 16 ordering by floppy disk we will produce masks based on the mask files generated by the mask file generating utility. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this mask file. thus, extreme care must be taken to verify the mask file in the submitted floppy disk. the submitted floppy disk must be 3.5-inch 2hd type and dos/v format. and the number of the mask files must be 1 in one floppy disk. file code (hexadecimal notation) mask file name .msk (equal or less than eight characters) ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill the appropriate mark specification form (52p4b for m37273m8-xxxsp) and attach to the mask rom confirmation form. 2/3 ] 3. comments (2) write the ascii codes that indicate the product name of m37273m8C to addresses 0000 16 to 000f 16 . addresses 0000 16 to 000f 16 store the product name. ascii codes m37273m8- are listed on the right. the addresses and data are in hexadecimal notation.
105 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 3/3 gzzCsh55C39b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37273m8-xxxsp mitsubishi electric ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 0 addresses 1412 16 and 1413 16 addresses 1612 16 and 1613 16 addresses 3812 16 and 3813 16 addresses 3a12 16 and 3a13 16 addresses 14fe 16 to 1501 16 addresses 16fe 16 to 1701 16 addresses 38fe 16 to 3901 16 addresses 3afe 16 to 3b01 16 character code ?a 16 left font right font line number line number = 0a 16 to 1d 16 character code = 00 16 to ff 16 (do not set 7f 16 and 80 16 .) font bit = 0 : left font 1 : right font example ) the font data ?0?(shaded area ) of the character code ?a 16 ?is stored in address 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 =2554 16 . font data must be stored in the proper osd rom address according to the following table. osd rom address of character font data osd rom address bit line number / character code / font bit font bit line number character code notes 1: the 80-byte addresses corresponding to the character code ?f 16 ?and ?0 16 ?in osd rom are the test data storning area. set ?f 16 ?to the area (we stores the test data to this area and the different data from ?f 16 ?is stored for the actual products.) the test data storing area : addresses 1000 16 + (4 + 2n) 5 100 16 + fe 16 to 1000 16 + (5 + 2n) 5 100 16 + 01 16 (n = 0 to 19) 2 : the character code ?9 16 ?is used for ?ransparent space?when displaying closed caption. therefore, set ?0 16 ?to the 40-byte addresses corresponding to the character code ?9 16 . the transparent space font data storing area : addresses 1000 16 + (4 + 2n) 5 100 16 + 12 16 to 1000 16 + (4 + 2n) 5 100 16 + 13 16 (n = 0 to 19)
106 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 gzzCsh55C40b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer M37273MF-XXXSP mitsubishi electric mask rom number receipt date: section head signature supervisor signature ] customer company name tel ( ) date : date issued issuance signature note : please fill in all items marked ] . submitted by supervisor ] 1. confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) (1) set ff 16 in the shaded area. 1/3 eprom address product nameascii code: 'm37273mf-' 2 7 c 1 0 1 0000 16 000f 16 1234567890123456 1 23456789012345 6 1234567890123456 osdrom data rom (60k) 1000 16 ffff 16 1234567890123456 1 23456789012345 6 1234567890123456 11400 16 1ffff 16 1234567890123456 1 23456789012345 6 1 23456789012345 6 1234567890123456 13bff 16
107 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 gzzCsh55C40b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer M37273MF-XXXSP mitsubishi electric addresses 0000 16 to 000f 16 store the product name. ascii codes m37273mf- are listed on the right. the addresses and data are in hexadecimal notation. note : if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. please make sure the data is written correctly. address 0000 16 m = 4d 16 0001 16 3 = 33 16 0002 16 7 = 37 16 0003 16 2 = 32 16 0004 16 7 = 37 16 0005 16 3 = 33 16 0006 16 m = 4d 16 0007 16 f = 46 16 address 0008 16 C = 2d 16 0009 16 ff 16 000a 16 ff 16 000b 16 ff 16 000c 16 ff 16 000d 16 ff 16 000e 16 ff 16 000f 16 ff 16 ordering by floppy disk we will produce masks based on the mask files generated by the mask file generating utility. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this mask file. thus, extreme care must be taken to verify the mask file in the submitted floppy disk. the submitted floppy disk must be 3.5-inch 2hd type and dos/v format. and the number of the mask files must be 1 in one floppy disk. file code (hexadecimal notation) mask file name .msk (equal or less than eight characters) ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill the appropriate mark specification form (52p4b for M37273MF-XXXSP) and attach to the mask rom confirmation form. 2/3 ] 3. comments (2) write the ascii codes that indicate the product name of m37273mfC to addresses 0000 16 to 000f 16 .
108 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 3/3 gzzCsh55C40b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer M37273MF-XXXSP mitsubishi electric font data must be stored in the proper osd rom address according to the following table. osd rom address of character font data line number = 0a 16 to 1d 16 character code = 00 16 to ff 16 (do not set 7f 16 and 80 16 .) font bit = 0 : left font 1 : right font ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 example ) the font data ?0?(shaded area ) of the character code ?a 16 ?is stored in address 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 =12554 16 . 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 0 ad16 1 osd rom address bit line number / character code / font bit font bit line number character code character code ?a 16 left font right font line number addresses 114fe 16 to 11501 16 addresses 116fe 16 to 11701 16 addresses 138fe 16 to 13901 16 addresses 13afe 16 to 13b01 16 addresses 11412 16 and 11413 16 addresses 11612 16 and 11613 16 addresses 13812 16 and 13813 16 addresses 13a12 16 and 13a13 16 notes 1: the 80-byte addresses corresponding to the character code ?f 16 ?and ?0 16 ?in osd rom are the test data storning area. set ?f 16 ?to the area (we stores the test data to this area and the different data from ?f 16 ?is stored for the actual products.) the test data storing area : addresses 11000 16 +(4+2n) 5 100 16 +fe 16 to11000 16 +(5+2n) 5 100 16 +01 16 (n=0 to 19) 2 : the character code ?9 16 ?is used for ?ransparent space?when displaying closed caption. therefore, set ?0 16 ?to the 40-byte addresses corresponding to the character code ?9 16 . the transparent space font data storing area : addresses 11000 16 +(4+2n) 5 100 16 +12 16 to 11000 16 +(4+2n) 5 100 16 +13 16 (n=0 to 19)
1 0 9 s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r w i t h c l o s e d c a p t i o n d e c o d e r a n d o n - s c r e e n d i s p l a y c o n t r o l l e r m 3 7 2 7 3 m 8 x x x s p , m 3 7 2 7 3 m f x x x s p m 3 7 2 7 3 e 8 s p , m 3 7 2 7 3 e f s p m i t s u b i s h i m i c r o c o m p u t e r s r e v . 1 . 0 1 8 . m a r k s p e c i f i c a t i o n f o r m
1 1 0 s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r w i t h c l o s e d c a p t i o n d e c o d e r a n d o n - s c r e e n d i s p l a y c o n t r o l l e r m 3 7 2 7 3 m 8 x x x s p , m 3 7 2 7 3 m f x x x s p m 3 7 2 7 3 e 8 s p , m 3 7 2 7 3 e f s p m i t s u b i s h i m i c r o c o m p u t e r s r e v . 1 . 0 1 9 . o n e t i m e p r o m v e r s i o n m 3 7 2 7 3 e 8 s p , m 3 7 2 7 3 e f s p m a r k i n g m 3 7 2 7 3 e 8 s p m 3 7 2 7 3 e f s p x x x x x x x x x x x x x x i s m i t s u b i s h i l o t n u m b e r
111 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 20. appendix pin configuration (top view) outline 52p4b 22 23 24 25 26 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 p0 6 /int2/ad4 x out p5 0 /h sync p5 1 /v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 av cc hlf v hold cv in cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /ad1/int3 p1 6 /ad2 p3 0 /ad5 p3 1 /ad6 reset p2 6 /osc1/x cin p2 7 /osc2/x cout v cc p1 7 /ad3 p6 3 p6 4 p6 5 p6 6 p6 7 p5 6 p5 7 p6 0 p6 1 p6 2 m37273m8-xxxsp,M37273MF-XXXSP m37273e8sp,m37273efsp
112 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 memory map 0000 16 00c0 16 00ff 16 sfr1 area ffff 16 ffde 16 ff00 16 0200 16 020f 16 sfr2 area 0300 16 00bf 16 0100 16 01ff 16 8000 16 rom correction function vector1: address 0300 16 vector2: address 0320 16 0320 16 rom (32k bytes) 087f 16 0800 16 osd ram (128 bytes) i see note j 05bf 16 3bff 16 1400 16 osd rom (10k bytes) ram (1152 bytes) ? m37273m8-xxxsp, m37273e8sp not used not used not used not used interrupt vector area special page note: refer to table 8.11.3 osd ram. 10000 16 1ffff 16 not used zero page
113 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 0000 16 00c0 16 00ff 16 sfr1 area ffff 16 ffde 16 ff00 16 0200 16 020f 16 sfr2 area not used 0300 16 00bf 16 0100 16 01ff 16 1000 16 rom correction function vector 1: address 0300 16 vector 2: address 0320 16 0320 16 rom (60k bytes) 10000 16 1ffff 16 087f 16 0800 16 osd ram (128 bytes) i see note j 06ff 16 13bff 16 11400 16 osd rom (10k bytes) ram (1472 bytes) ? M37273MF-XXXSP, m37273efsp not used not used interrupt vector area special page note: refer to table 8.11.3 osd ram. not used not used zero page
114 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 memory map of special function register (sfr) n s f r 1 a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) d 0 1 6 d 1 1 6 d 2 1 6 d 3 1 6 d 4 1 6 d 5 1 6 d 6 1 6 d 7 1 6 d 8 1 6 d 9 1 6 d a 1 6 d b 1 6 d c 1 6 d d 1 6 d e 1 6 d f 1 6 c 0 1 6 c 1 1 6 c 2 1 6 c 3 1 6 c 4 1 6 c 5 1 6 c 6 1 6 c 7 1 6 c 8 1 6 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 c a 1 6 a d d r e s s p o r t p 5 ( p 5 ) c a p t i o n d a t a r e g i s t e r 3 ( c d 3 ) c a p t i o n d a t a r e g i s t e r 4 ( c d 4 ) o s d c o n t r o l r e g i s t e r ( o c ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( d 1 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) b l o c k c o n t r o l r e g i s t e r 1 ( b c 1 ) b l o c k c o n t r o l r e g i s t e r 2 ( b c 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 ( v p 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 ( v p 2 ) w i n d o w r e g i s t e r 1 ( w n 1 ) i n t e r r u p t i n p u t p o l a r i t y c o n t r o l r e g i s t e r ( r e ) b 7b 0 b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t b 7b 0 o s d p o r t c o n t r o l r e g i s t e r ( p f ) w i n d o w r e g i s t e r 2 ( w n 2 ) i / o p o l a r i t y c o n t r o l r e g i s t e r ( p c ) r a s t e r c o l o r r e g i s t e r ( r c ) : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? < s t a t e i m m e d i a t e l y a f t e r r e s e t > : 1 i m m e d i a t e l y a f t e r r e s e t : f i x t h i s b i t t o 0 ( d o n o t w r i t e 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t h i s b i t t o 1 ( d o n o t w r i t e 0 ) n a m e : 1 0 ? 0 0 1 6 ? 0 0 1 6 ? 0 0 1 6 ??000000 ? ? ? ? ? ? p f 2p f 3p f 4p f 5p f 7 ? ? ? ? i n t 1i n t 2i n t 3 ? p 3 0p 3 1 p 3 0 dp 3 1 dp 3 0 ct 3 s cp 3 1 c ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 4 0 1 6 o c 4 o c 5o c 2o c 3o c 0o c 1 o c 6 b c 1 0b c 1 1 b c 1 2b c 1 3b c 1 4b c 1 5 b c 1 6b c 1 7 b c 2 0b c 2 1b c 2 2b c 2 3b c 2 4b c 2 5 b c 2 6b c 2 7 v p 1 0v p 1 1v p 1 2v p 1 3v p 1 4v p 1 5 v p 1 6v p 1 7 v p 2 0v p 2 1v p 2 2v p 2 3v p 2 4v p 2 5 v p 2 6v p 2 7 w n 1 0w n 1 1w n 1 2w n 1 3w n 1 4w n 1 5w n 1 6w n 1 7 w n 2 0w n 2 1w n 2 2w n 2 3w n 2 4w n 2 5w n 2 6w n 2 7 r c 0r c 1r c 2r c 7 0 00 r c 3 r c 4 0 0 1 6 0 0 1 6 c d l 2 0c d l 2 1c d l 2 2c d l 2 3c d l 2 4c d l 2 5 c d l 2 6c d l 2 7 c d h 2 0c d h 2 1c d h 2 2c d h 2 3c d h 2 4c d h 2 5 c d h 2 6c d h 2 7 h p 4 h p 5 h p 2h p 3 h p 0 h p 1 h p 6 p c 4 p c 5 p c 2p c 3 p c 0 p c 1 p c 6 0 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 0 0 1 6 ( s e e n o t e 1 ) 0 0 1 6 ( s e e n o t e 2 ) n o t e s 1 : t h i s i s o n l y m 3 7 2 7 3 m f - x x x s p a n d m 3 7 2 7 3 e 8 s p . 2: a s f o r m 3 7 2 7 3 m 8 - x x x s p a n d m 3 7 2 7 3 e 8 s p , t h e r e s e t v a l u e i s ? ( i n d e t e r m i n a t e ) . p o r t p 6 ( p 6 )
115 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e 7 1 6 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 a d d r e s s s e r i a l i / o r e g i s t e r ( s i o ) a - d c o n t r o l r e g i s t e r 1 ( a d 1 ) t i m e r 5 ( t 5 ) t i m e r 6 ( t 6 ) t i m e r 1 ( t 1 ) c a p t i o n d a t a r e g i s t e r 1 ( c d 1 ) c a p t i o n p o s i t i o n r e g i s t e r ( c p s ) d a t a s l i c e r t e s t r e g i s t e r 2 c l o c k r u n - i n d e t e c t r e g i s t e r ( c r d ) d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) r e g i s t e r d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r m o d e r e g i s t e r 1 ( t m 1 ) t i m e r m o d e r e g i s t e r 2 ( t m 2 ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) d a t a s l i c e r t e s t r e g i s t e r 1 s y n c h r o n o u s s i g n a l c o u n t e r r e g i s t e r ( h c ) a - d c o n t r o l r e g i s t e r 2 ( a d 2 ) c p u m o d e r e g i s t e r ( c p u m ) b 7b 0 b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t b 7b 0 n s f r 1 a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) c a p t i o n d a t a r e g i s t e r 2 ( c d 2 ) s e r i a l i / o m o d e r e g i s t e r ( s m ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? < s t a t e i m m e d i a t e l y a f t e r r e s e t > : 1 i m m e d i a t e l y a f t e r r e s e t : f i x t h i s b i t t o 0 ( d o n o t w r i t e 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t h i s b i t t o 1 ( d o n o t w r i t e 0 ) n a m e : 1 0 t m 2 0 t m 2 1t m 2 2t m 2 3t m 2 4 t m 1 0 t m 1 1t m 1 2t m 1 3t m 1 4 c m 2 t m 1 r t m 2 rt m 3 rt m 4 ro s d rv s c r i n 3 r c k 0 i n 1 r d s r s 1 r t m 1 e t m 2 et m 3 et m 4 eo s d ev s c e i n 1 e d s es 1 ei n 2 e t m 2 5 0 0 1 6 f f 1 6 0 7 1 6 f f 1 6 0 7 1 6 0 7 1 6 t m 1 5t m 1 6t m 1 7 t m 2 6t m 2 7 ? s a d 0s a d 1s a d 2s a d 3s a d 4s a d 5s a d 6r b w l r ba d 0a a sa lp i nb bt r xm s t b c 0b c 1b c 2e s oa l s b s e l 0b s e l 1 c c r 0c c r 1c c r 2c c r 3c c r 4a c k 0 0 1 6 0 0 1 6 0 0 1 6 c k r i n 2 ri i c r t m 5 6 r i n 3 e c k ei i c e t m 5 6 et m 5 6 c 00 c m 7c m 5c m 6 s m 0s m 1s m 2s m 3 a d c 1 0a d c 1 1a d c 1 2a d c 1 4 a d c 2 0a d c 2 1a d c 2 2a d c 2 5 s m 5s m 6 a d c 2 4a d c 2 3 1 0 b i t s a d f a s t m o d e ? 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 d s c 1 0d s c 1 1d s c 1 2 d s c 2 0 d s c 2 3d s c 2 4d s c 2 5 c r d 3c r d 4c r d 5c r d 6c r d 7 d p s 3d p s 4d p s 5d p s 6d p s 7 c p s 0c p s 3c p s 4c p s 5c p s 1c p s 2c p s 6c p s 7 h c 0h c 3h c 4h c 5h c 1h c 2 0? 0? 0 ? ?? 00 0 ? 01100 01 1 00 00 1 0 1 00 00 0 0 1 6 c d h 1 0c d h 1 3c d h 1 4c d h 1 5c d h 1 1c d h 1 2c d h 1 6c d h 1 7 c d l 1 0c d l 1 3c d l 1 4c d l 1 5c d l 1 1c d l 1 2c d l 1 6c d l 1 7 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 d 1d 2d 3d 4d 5d 6d 7d 0 00 00?00 0 0 0 0 01 0 0? a c k b i t 0 9 1 6 3 c 1 6
116 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 2 0 0 1 6 2 0 1 1 6 2 0 2 1 6 2 0 3 1 6 2 0 4 1 6 2 0 5 1 6 2 0 6 1 6 2 0 7 1 6 2 0 8 1 6 2 0 9 1 6 2 0 b 1 6 2 0 c 1 6 2 0 d 1 6 2 0 e 1 6 2 0 f 1 6 2 0 a 1 6 a d d r e s s p w m m o d e r e g i s t e r 2 ( p m 2 ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) p w m 2 r e g i s t e r ( p w m 2 ) p w m 4 r e g i s t e r ( p w m 4 ) p w m 5 r e g i s t e r ( p w m 5 ) r e g i s t e r p w m 0 r e g i s t e r ( p w m 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m m o d e r e g i s t e r 1 ( p m 1 ) r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) b 7b 0 b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t b 7b 0 n s f r 2 a r e a ( a d d r e s s e s 2 0 0 1 6 t o 2 0 f 1 6 ) p w m 3 r e g i s t e r ( p w m 3 ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? < s t a t e i m m e d i a t e l y a f t e r r e s e t > : 1 i m m e d i a t e l y a f t e r r e s e t : f i x t h i s b i t t o 0 ( d o n o t w r i t e 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t h i s b i t t o 1 ( d o n o t w r i t e 0 ) n a m e : 1 0 0 0 1 6 ? ? ? ? ? ? ? 0 0 1 6 p m 1 3 ? ?? ?0 ? ? 0 p m 1 0 p m 2 5p m 2 4p m 2 3p m 2 2p m 2 1p m 2 0 r c 0 r c 1 ? 0 0 1 6 0 0 1 6 0 0 1 6 ? 0 0 1 6 00 0 0 1 6 0 0 1 6
117 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i z cdbtv n?? ????? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0
118 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e b i t a t t r i b u t e s ( n o t e 1 ) ( n o t e 2 ) b i t p o s i t i o n 2 : b i t a t t r i b u t e s t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : b i t i n w h i c h n o t h i n g i s a s s i g n e d n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 0 a f t e r r e s e t r e l e a s e 1 1 a f t e r r e s e t r e l e a s e i n d e t e r m i n a t e i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e r e a d e n a b l e d r e a d d i s a b l e d r r r e a d w r i t e e n a b l e d w r i t e d i s a b l e d 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . w w r i t e w ] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e rw c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m ef u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( s e e n o t e ) ( c m 2 ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 1 . 6 , 7 0 c l o c k s w i t c h b i t s ( c m 6 , c m 7 ) 0 0 : f ( x i n ) = 8 m h z 0 1 : f ( x i n ) = 1 2 m h z 1 0 : f ( x i n ) = 1 6 m h z 1 1 : d o n o t s e t b 7 b 6 c p u m o d e r e g i s t e r ( c p u m ) ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw rw r w rw < e x a m p l e >
119 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 port p3 direction register (p3d) [address 00c7 16 ] b name functions after reset rw port p3 direction register 0 0 : port p3 0 input mode 1 : port p3 0 output mode 0 1 0 : port p3 1 input mode 1 : port p3 1 output mode 0 2 0 : cmos output 1 : n-channel open-drain output 0 0 port p3 direction register nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. rw rw rw r 4, 5, 7 port p3 0 output structure selection bit (p30c) 3 0 : cmos output 1 : n-channel open-drain output 0rw port p3 1 output structure selection bit (p30c) 6 refer to timer section.timer 3 count source selection bit (t3sc) 0rw b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (pid) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 0 0 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 3 0 : port pi 3 input mode 1 : port pi 3 output mode 0 4 0 : port pi 4 input mode 1 : port pi 4 output mode 0 5 0 : port pi 5 input mode 1 : port pi 5 output mode 0 6 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw address 00c1 16 , 00c3 16 , 00c5 16 address 00c7 16
120 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 osd control register (oc) [address 00d0 16 ] b name functions after reset r w osd control register 0 osd control bit (oc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 automatic solid space control bit (oc1) 0 : off 1 : on 0 2 0 : off 1 : on 0 0 4 osd mode clock selection bit (oc4) 0 window control bit (oc2) rw rw rw rw rw 3 0 : data slicer clock 1 : clock from osc1 pin cc mode clock selection bit (oc3) 5, 6 osc1 clock selection bit (oc5, oc6) 0 0: 32 khz oscillating 0 1: do not set. 1 0: lc oscillating, ceramic oscillating 1 1: do not set. b6 b5 0 : data slicer clock 1 : clock from osc1 pin 7 fix this bit to ?. 0rw 0rw 0 note: even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . b 7b 6b 5b 4b 3b 2b 1b 0 o s d p o r t c o n t r o l r e g i s t e r ( p f ) [ a d d r e s s 0 0 c b 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w o s d p o r t c o n t r o l r e g i s t e r 0 2 0 30 : g s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t 0 0 f i x t h e s e b i t s t o 0 . r rw rw rw 0 , 1 p o r t p 5 3 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 3 ) 4 0 : b s i g n a l o u t p u t 1 : p o r t p 5 4 o u t p u t 0rw p o r t p 5 4 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 4 ) 0rw 0 : r s i g n a l o u t p u t 1 : p o r t p 5 2 o u t p u t p o r t p 5 2 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 2 ) 5 0 : o u t 1 s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t p o r t p 5 5 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 5 ) 70 : p o r t p 1 0 o u t p u t 1 : o u t 2 s i g n a l o u t p u t p o r t p 1 0 o u t p u t s i g n a l s e l e c t i o n b i t ( p f 7 ) 00 0 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . r 6 address 00cb 16 address 00d0 16
121 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 block control register i (bci) (i=1, 2) [addresses 00d2 16 and 00d3 16 ] block control register i 0, 1 display mode selection bits (bci0, bci1) (see note 1) indeterminate 2, 3 dot size selection bits (bci2, bci3) b4 b3 b2 pre-divide ratio dot size 4 pre-divide ratio selection bit (bci4) 5 7 window top/bottom boundary control bit (bci7) notes 1: bit ra3 of osd ram controls out1 output when bit 5 is ?. bit ra3 of osd ram controls out2 output when bit 5 is ?. 2: tc is osd clock cycle divided in pre-divide circuit. 3: h is h sync . out1/out2 output control bit (bci5) (see note 1) 0: out1 output control 1: out2 output control 6 vertical display start position control bit (bci6) bc16: block 1 bc26: block 1 b1 b0 0 0: display off 0 1: cc mode 1 0: osd mode (border off) 1 1: osd mode (border on) 00 01 10 11 00 01 10 11 0 1 5 2 5 3 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h bc17: window top boundary bc27: window bottom boundary b name functions after reset rw rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw address 00d1 16 address 00d2 16 , 00d3 16 b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00d1 16 ] b name horizontal position register 7 horizontal display start position control bits (hp0 to hp6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. functions after reset r w horizontal display start positions 128 steps (00 16 to 7f 16 ) (1 step is 4t osc ) 0 0 rw r 0 to 6 note: the setting value synchronizes with the v sync .
122 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 address 00d4 16 , 00d5 16 address 00d6 16 address 00d7 16 b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w vertical position register i vertical position register i (vpi) (i = 1 and 2) [addresses 00d4 16 , 00d5 16 ] b name functions after reset rw inderterminate vertical display start position control bits (vpi0 to vpi7) (see note) vertical display start position = t h 5 (bci6 5 16 2 + n) (n: setting value, t h : h sync cycle, bci6: bit 6 of block control register i) note: set values except ?0 16 to vpi when bci6 is ?. b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 1 window register 1 (wn1) [address 00d6 16 ] b name functions after reset rw inderterminate window top boundary control bits (wn10 to wn17) window top border position = t h 5 (bc17 5 16 2 + n) (n: setting value, t h : h sync cycle, bc17: bit 7 of block control register 1) notes 1: set values except ?0 16 ?to wn1 when bc17 is ?. 2: set values fit for the following condition: wn1 < wn2. b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 2 window register 2 (wn2) [address 00d7 16 ] b name functions after reset rw inderterminate window bottom boundary control bits (wn20 to wn27) window bottom border position = t h 5 (bc27 5 16 2 + n) (n: setting value, t h : h sync cycle, bc27: bit 7 of block control register 2) note: set values fit for the following condition: wn1 < wn2.
123 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 0 : at even field at odd field 1 : at even field at odd field b7 b6 b5 b4 b3 b2 b1 b0 i/o polarity control register (pc) [address 00d8 16 ] b name functions after reset r w i/o polarity control register 0h sync input polarity switch bit (pc0) 0 : positive polarity input 1 : negative polarity input 0 1 0 : positive polarity input 1 : negative polarity input 0 2 r, g, b output polarity switch bit (pc2) 0 : positive polarity output 1 : negative polarity output 0 3 out1 output polarity switch bit (pc3) 0 : positive polarity output 1 : negative polarity output 0 4 out2 output polarity switch bit (pc4) 0 : positive polarity output 1 : negative polarity output 0 5 display dot line selection bit (pc5) (see note) 0 6 field determination flag (pc6) 0 : even field 1 : odd field 1 7 0 v sync input polarity switch bit (pc1) rw rw rw rw rw rw r rw fix this bit to 0. note: refer to the corresponding figure (8.11.14). 0 b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 00d9 16 ] b name functions after reset r w raster color register 0 raster color r control bit (rc0) 0 : no output 1 : output 0 1 raster color g control bit (rc1) 0 : no output 1 : output 0 2 0 : no output 1 : output 0 0 4 raster color out2 control bit (rc4) 0 raster color b control bit (rc2) rw rw rw rw rw 3 0 : no output 1 : output raster color out1 control bit (rc3) 5, 6 0 : no output 1 : output 7 fix these bits to ?. 0rw 0rw 0 note: either osd clock source or 32 khz oscillating clock is selected by bits 5 and 6 of the osd control register. 0 port function selection bit (rc7) 0 : osc1/x cin , osc2/x cout 1 : p2 6 , p2 7 address 00d9 16 address 00d8 16
124 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register (re) [address 00dc 16 ] b name functions after reset r w interrupt input polarity register int1 polarity switch bit (int1) 0 0 0 0 : positive polarity 1 : negative polarity 0 4 0 : positive polarity 1 : negative polarity 5 4 to 7 int2 polarity switch bit (int2) int3 polarity switch bit (int3) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 rw rw rw r 0 : positive polarity 1 : negative polarity b 7b 6b 5b 4b 3b 2b 1b 0 d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) [ a d d r e s s 0 0 e 0 1 6 ] d a t a s l i c e r c o n t r o l r e g i s t e r 1 00 rw 0rw 2r e f e r e n c e c l o c k s o u r c e s e l e c t i o n b i t ( d s c 1 2 ) 0 : v i d e o s i g n a l 1 : h s y n c s i g n a l 0r w 0rw 0 rw 11 0 : s t o p p e d 1 : o p e r a t i n g d a t a s l i c e r a n d t i m i n g s i g n a l g e n e r a t i n g c i r c u i t c o n t r o l b i t ( d s c 1 0 ) f i x t h e s e b i t s t o 0 . 3 , 4 000 10 : f 2 1 : f 1 s e l e c t i o n b i t o f d a t a s l i c e r e f e r e n c e v o l t a g e g e n e r a t i n g f i e l d ( d s c 1 1 ) f i x t h e s e b i t s t o 1 . 5 , 6 d e f i n i t i o n o f f i e l d s 1 ( f 1 ) a n d 2 ( f 2 ) h s e p v s e p f 1 : h s e p v s e p f 2 : b a f t e r r e s e t r w n a m ef u n c t i o n s 0rw f i x t h i s b i t t o 0 . 7 address 00dc 16 address 00e0 16
125 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 clock run-in detect register (crd) [address 00e4 16 ] r w clock run-in detect register 0 to 2 0r test bits 3 to 7 number of reference clocks to be counted in one clock run-in pulse period. clock run-in detection bit (crd3 to crd7) 0r read-only b after resetfunctionsname b 7b 6b 5b 4b 3b 2b 1b 0 d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) [ a d d r e s s 0 0 e 1 1 6 ] r w d a t a s l i c e r c o n t r o l r e g i s t e r 2 0i n d e t e r m i n a t e r 1 0r w i n d e t e r m i n a t er i n d e t e r m i n a t er 01 0 : d a t a i s n o t l a t c h e d y e t a n d a c l o c k - r u n - i n i s n o t d e t e r m i n e d . 1 : d a t a i s l a t c h e d a n d a c l o c k - r u n - i n i s d e t e r m i n e d . c a p t i o n d a t a l a t c h c o m p l e t i o n f l a g 1 ( d s c 2 0 ) f i x t h i s b i t t o 1 . 2r e a d - o n l y t e s t b i t 30 : f 2 1 : f 1 f i e l d d e t e r m i n a t i o n f l a g ( d s c 2 3 ) 40 : m e t h o d ( 1 ) 1 : m e t h o d ( 2 ) v e r t i c a l s y n c h r o n o u s s i g n a l ( v s e p ) g e n e r a t i n g m e t h o d s e l e c t i o n b i t ( d s c 2 4 ) 0rw 50 : m a t c h 1 : m i s m a t c h v - p u l s e s h a p e d e t e r m i n a t i o n f l a g ( d s c 2 5 ) i n d e t e r m i n a t er 6 0 rw f i x t h i s b i t t o o . b a f t e r r e s e t f u n c t i o n sn a m e d e f i n i t i o n o f f i e l d s 1 ( f 1 ) a n d 2 ( f 2 ) h s e p v s e p f 1 : h s e p v s e p f 2 : r 7 r e a d - o n l y t e s t b i t i n d e t e r m i n a t e address 00e4 16 address 00e1 16
126 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7b 6b 5b 4b 3b 2b 1b 0 d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) [ a d d r e s s 0 0 e 5 1 6 ] d a t a c l o c k p o s i t i o n r e g i s t e r 01 rw f i x t h i s b i t t o 0 . 1f i x t h i s b i t t o 1 . 0rw 10 0 b a f t e r r e s e t f u n c t i o n s n a m e rw 3 d a t a c l o c k p o s i t i o n s e t b i t s ( d p s 3 t o d p s 7 ) 1rw 4 t o 7 0 2f i x t h i s b i t t o 0 . 0rw b 7b 6b 5b 4b 3b 2b 1b 0 c a p t i o n p o s i t i o n r e g i s t e r ( c p s ) [ a d d r e s s 0 0 e 6 1 6 ] c a p t i o n p o s i t i o n r e g i s t e r 0 t o 4 0 rw 0r w c a p t i o n p o s i t i o n b i t s ( c p s 0 t o c p s 4 ) 6 , 7r e f e r t o t h e c o r r e s p o n d i n g t a b l e ( t a b l e 8 . 1 0 . 1 ) . s l i c e l i n e m o d e s p e c i f i c a t i o n b i t s ( i n 1 f i e l d ) ( c p s 6 , c p s 7 ) 50 : d a t a i s n o t l a t c h e d y e t a n d a c l o c k - r u n - i n i s n o t d e t e r m i n e d . 1 : d a t a i s l a t c h e d a n d a c l o c k - r u n - i n i s d e t e r m i n e d . c a p t i o n d a t a l a t c h c o m p l e t i o n f l a g 2 ( c p s 5 ) i n d e t e r m i n a t e r b a f t e r r e s e t f u n c t i o n sn a m e rw b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (hc) [address 00e9 16 ] r w sync pulse counter register 0 to 4 0r 6, 7 0 r count value (hc0 to hc4) 5 0rw count source (hc5) 0: h sync signal 1: composite sync signal b after reset functionsname nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. address 00e5 16 address 00e6 16 address 00e9 16
127 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 e b 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw s e r i a l i / o m o d e r e g i s t e r 0 , 1 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 o r f ( x c i n ) / 4 0 1 : f ( x i n ) / 1 6 o r f ( x c i n ) / 1 6 1 0 : f ( x i n ) / 3 2 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 p o r t f u n c t i o n s e l e c t i o n b i t ( s m 3 ) 4 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0 0 : p 2 0 , p 2 1 1 : s c l k , s o u t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : l s b f i r s t 1 : m s b f i r s t 6 f i x t h i s b i t t o 0 . 0 0 0 0 0 0 t r a n s f e r c l o c k i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n 1 : i n p u t s i g n a l f r o m s o u t p i n rw rw rw r w rw rw 0 7 f i x t h i s b i t t o 0 . 0r w b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n t r o l r e g i s t e r 1 ( a d 1 ) [ a d d r e s s 0 0 e c 1 6 ] b a f t e r r e s e t rw a - d c o n t r o l r e g i s t e r 1 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d c 1 0 t o a d c 1 2 ) n a m ef u n c t i o n s b 2 b 1 b 0 0 0 0 : a d 1 0 0 1 : a d 2 0 1 0 : a d 3 0 1 1 : a d 4 1 0 0 : a d 5 1 0 1 : a d 6 1 1 0 : 1 1 1 : 4 s t o r a g e b i t o f c o m p a r i s o n r e s u l t ( a d c 1 4 ) 0 : i n p u t v o l t a g e < r e f e r e n c e v o l t a g e 1 : i n p u t v o l t a g e > r e f e r e n c e v o l t a g e 0 i n d e t e r m i n a t e 0 d o n o t s e t . 3t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . rw rw r 0 5 t o 7 n o t h i n g i s a s s i g n e d . t h i s b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r address 00ec 16 address 00eb 16
128 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2 (ad2) [address 00ed 16 ] b after reset rw a-d control register 2 0 to 5 6, 7 0 0 name functions d-a converter set bits (adc20 to adc25) b0b1b2 b3 b4 b5 nothing is assigned. these bits are write disable bits. when these bits are reed out, the values are ?0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128vcc : 5/128vcc : 123/128vcc : 125/128vcc : 127/128vcc : 1/128vcc rw r b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tm10) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 5 of tm1 timer 2 count source selection bit 1 (tm11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tm12) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop timer 2 count source selection bit 2 (tm14) r 0 0 0 0 0 wr wr wr wr wr 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 timer 5 count source selection bit 2 (tm16) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 timer 6 internal count source selection bit (tm17) 0w r0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. address 00ed 16 address 00f4 16
129 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset rw timer mode register 2 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0rw 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 0 0 : f(x in )/16 or f(x cin )/16 (see note) 0 1 : f(x cin ) 1 0 : 11 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 0 0 : timer 3 overflow signal 0 1 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x in )/2 or f(x cin )/2 (see note) 1 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. address 00f5 16 address 00f6 16 b 7b 6b 5b 4b 3b 2b 1b 0 i c d a t a s h i f t r e g i s t e r 1 ( s 0 ) [ a d d r e s s 0 0 f 6 1 6 ] b f u n c t i o n s a f t e r r e s e trw i c d a t a s h i f t r e g i s t e r 0 t o 7 t h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a . i n d e t e r m i n a t e 2 2 n o t e : 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n a m e d 0 t o d 7rw
130 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7b 6b 5b 4b 3b 2b 1b 0 0r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 f 7 1 6 ] b n a m e f u n c t i o n s 0 0 a f t e r r e s e t r w r r w b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 f 8 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : s l a v e r e c i e v e m o d e 0 1 : s l a v e t r a n s m i t m o d e 1 0 : m a s t e r r e c i e v e m o d e 1 1 : m a s t e r t r a n s m i t m o d e 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b u s f r e e 1 : b u s b u s y b u s b u s y f l a g ( b b ) 0 : i n t e r r u p t r e q u e s t i s s u e d 1 : n o i n t e r r u p t r e q u e s t i s s u e d i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n o t d e t e c t e d 1 : d e t e c t e d a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : a d d r e s s m i s m a t c h 1 : a d d r e s s m a t c h s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o g e n e r a l c a l l d e t e c t e d 1 : g e n e r a l c a l l d e t e c t e d g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l a s t b i t = 0 1 : l a s t b i t = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) address 00f7 16 address 00f8 16
131 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7b 6b 5b 4b 3b 2b 1b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g m o d e 1 : f r e e d a t a f o r m a t 5a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d a d d r e s s 0 0 f 9 1 6 ) i 2 c c o n t r o l r e g i s t e r b n a m e f u n c t i o n s a f t e r r e s e t r w n o t e : w h e n u s i n g p o r t s p 1 1 - p 1 4 a s i c - b u s i n t e r f a c e , t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m c m o s o u t p u t t o n - c h a n n e l o p e n - d r a i n o u t p u t . 2 2 r w r w r w r w r w b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00fa 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0: standard clock mode 1: high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0: ack is returned. 1: ack is not returned. 0: no ack clock 1: ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 33303 setup disabled 25004 100 400 (see note) 05 83.3 16606 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 4000khz in the high-speed clock mode, the duty is as below . ??period : ??period = 3 : 2 in the other cases, the duty is as below. ??period : ??period = 1 : 1 setup value of ccr4 ccr0 rw rw rw rw address 00f9 16 address 00fa 16
132 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3 t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4o s d i n t e r r u p t r e q u e s t b i t ( o s d r ) 5v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 i n t 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( v s c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ? r r r r r r r r n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e s e t rw c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m ef u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( c m 2 ) ( s e e n o t e ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1 6 0 m a i n c l o c k ( x i n e x o u t ) s t o p b i t ( c m 6 ) c p u m o d e r e g i s t e r ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw r w r w rw x c o u t d r i v a b i l i t y s e l e c t i o n b i t ( c m 5 ) 0 : l o w d r i v e 1 : h i g h d r i v e 0 : o s c i l l a t i n g 1 : s t o p p e d 7 0 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( c m 7 ) rw 0 : x i n e x o u t s e l e c t e d ( h i g h - s p e e d m o d e ) 1 : x c i n e x c o u t s e l e c t e d ( h i g h - s p e e d m o d e ) n o t e : t h i s b i t i s s e t t o 1 a f t e r t h e r e s e t r e l e a s e . address 00fb 16 address 00fc 16
133 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7b 6 b 5 b 4b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i n i r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 d a t a s l i c e r i n t e r r u p t r e q u e s t b i t ( d s r ) 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i n 2 r ) 5 7f i x t h i s b i t t o 0 . 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . 0 0 ] 0 0 ] 0 ] 0 ] 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 6 ] r r r r ] r r ] r w f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( c k r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d m u l t i - m a s t e r i 2 c - b u s i n t e r r u p t r e q u e s t b i t ( i i c r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 6 t i m e r 5 6 i n t e r r u p t r e q u e s t b i t ( t m 5 6 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] r b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t c o n t r o l r e g i s t e r 1 0 t i m e r 1 i n t e r r u p t e n a b l e b i t ( t m 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 t i m e r 2 i n t e r r u p t e n a b l e b i t ( t m 2 e ) 2 t i m e r 3 i n t e r r u p t e n a b l e b i t ( t m 3 e ) 3 4 o s d i n t e r r u p t e n a b l e b i t ( o s d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 0 rw rw rw rw rw r? 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . t i m e r 4 i n t e r r u p t e n a b l e b i t ( t m 4 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 v s y n c i n t e r r u p t e n a b l e b i t ( v s c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw 6 i n t 3 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i n 3 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw address 00fd 16 address 00fe 16
134 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t c o n t r o l r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i n 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 d a t a s l i c e r i n t e r r u p t e n a b l e b i t ( d s e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i n 2 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 rw rw rw rw rw f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( c k e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t e n a b l e b i t ( i i c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw 6 t i m e r 5 ? 6 i n t e r r u p t e n a b l e b i t ( t m 5 6 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0rw 7 t i m e r 5 ? 6 i n t e r r u p t s w i t c h b i t ( t m 5 6 c ) 0 : t i m e r 5 1 : t i m e r 6 0rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m m o d e r e g i s t e r 1 ( p m 1 ) [ a d d r e s s 0 2 0 8 1 6 ] b a f t e r r e s e t rw p w m m o d e r e g i s t e r 1 0 1 , 2 3 0 n a m ef u n c t i o n s p w m o u t p u t p o l a r i t y s e l e c t i o n b i t ( p m 1 3 ) i n d e t e r m i n a t e 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y r w r rw p w m c o u n t s s o u r c e s e l e c t i o n b i t ( p m 1 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p 4 t o 7 i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r address 00ff 16 address 0208 16
135 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pm2) [address 0209 16 ] b after reset rw pwm mode register 2 0 1 2 3 4 0 name functions p0 0 /pwm0 output selection bit (pm20) 0 : p0 0 output 1 : pwm0 output p0 2 /pwm2 output selection bit (pm22) 0 : p0 2 output 1 : pwm2 output p0 3 /pwm3 output selection bit (pm23) 0 : p0 3 output 1 : pwm3 output p0 4 /pwm4 output selection bit (pm24) 0 : p0 4 output 1 : pwm4 output 5 p0 5 /pwm5 output selection bit (pw25) 0: p0 5 output 1: pwm5 output 6, 7 fix these bits to ?. p0 1 /pwm1 output selection bit (pm21) 0 : p0 1 output 1 : pwm1 output 0 0 0 0 0 0 rw rw rw rw rw rw rw 00 b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 020e 16 ] b after reset rw rom correction enable register 0 vector 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 vector 2 enable bit (rc1) 0: disabled 1: enabled 2 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?.? 0 0 0 rw rw r address 0209 16 address 020e 16
136 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers rev . 1.0 22. package outline sdip52-p-600-1.78 weight(g) C jedec code 5.1 eiaj package code lead material alloy 42/cu alloy 52p4b plastic 52pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.4 0 .5 0.6 0.9 1 .0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 1 .778 15.24 3.0 0 e15 e e 5.5 e e 1 52 27 26 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d
single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37273m8Cxxxsp, m37273mfCxxxsp m37273e8sp, m37273efsp mitsubishi microcomputers ? 1999 mitsubishi electric corp. new publication, effective sep. 1999. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
rev. rev. no. date 1.0 first edition of pdf file 9909 (1/1) revision description revision history m37273m8-xxxsp, M37273MF-XXXSP m37273e8sp, m37273efsp (rev. 1.0) data sheet

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